mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 02:47:02 +02:00
Resolve GPU-selected raw buffer descriptors through shared RDNA2 addressing
Co-authored-by: Bipin <87369440+bipinkrish@users.noreply.github.com>
This commit is contained in:
nmzik
@@ -132,12 +132,23 @@ void ValidateNativeProgram(const IR::Program& program) {
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program.memory_info[index].planning_only;
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});
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};
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const auto indirect_buffer_handle = [&](const IR::Inst& handle) {
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return program.info.uses_dma && handle.NumArgs() == 4u && !handle.Uses().empty() &&
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std::ranges::all_of(handle.Uses(), [&](const IR::Use& use) {
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if (IR::BufferAccessOf(use.user->GetOpcode()) != IR::BufferAccess::Read) {
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return false;
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}
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const auto index = use.user->Flags<IR::MemoryFlags>().index;
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return index < program.memory_info.size() &&
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program.memory_info[index].kind == IR::ResourceKind::IndirectBuffer;
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});
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};
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for (const auto* block: program.blocks) {
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for (const auto& inst: *block) {
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const auto dense = inst.Flags<uint32_t>();
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switch (inst.GetOpcode()) {
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case IR::ValueOpcode::GetBufferResource:
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if (planning_only_handle(inst)) {
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if (planning_only_handle(inst) || indirect_buffer_handle(inst)) {
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break;
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}
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if (dense >= program.info.buffers.size()) {
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@@ -212,6 +223,9 @@ Emitter::SpirvRequirements Emitter::AnalyzeProgramRequirements(const IR::Program
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Fail(program, "buffer operation has invalid memory metadata");
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}
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const auto& memory = program.memory_info[memory_index];
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if (memory.kind == IR::ResourceKind::IndirectBuffer) {
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requirements.subgroup_local_invocation_id = true;
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}
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if (memory.kind == IR::ResourceKind::Buffer) {
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if (memory.resource >= program.info.buffers.size()) {
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Fail(program, "buffer operation has invalid resource metadata");
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@@ -27,61 +27,66 @@ uint32_t EmitDsMaskedLaneRead(EmitterState& state, uint32_t source, uint32_t tar
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return Select(state, TypeU32(state), source_active, shuffled, ConstantU32(state, 0));
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}
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uint32_t BufferByteAddress(ValueEmitContext& ctx, const IR::Inst& inst, const IR::MemoryInfo& mem,
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uint32_t index, uint32_t offset, uint32_t soffset) {
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auto& state = ctx.state;
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const uint32_t packed = StorageBufferPackedStride(state, mem);
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const uint32_t stride = packed & 0x3fffu;
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const bool swizzle = stride != 0u && ((packed >> 14u) & 1u) != 0u;
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if (((packed >> 20u) & 1u) != 0u) {
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const auto lane = Binary(state, spv::OpBitwiseAnd, TypeU32(state),
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EmitSubgroupLocalInvocationId(state), ConstantU32(state, 63));
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index = Binary(state, spv::OpIAdd, TypeU32(state), index, lane);
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}
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if (mem.offset != 0u) {
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offset = Binary(state, spv::OpIAdd, TypeU32(state), offset, ConstantU32(state, mem.offset));
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}
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struct BufferAddress {
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uint32_t offset;
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uint32_t byte;
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};
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uint32_t address = 0;
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if (!swizzle) {
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if (stride == 0u) {
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address = offset;
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} else {
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const auto indexed = stride == 1u ? index
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: Binary(state, spv::OpIMul, TypeU32(state), index,
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ConstantU32(state, stride));
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address = Binary(state, spv::OpIAdd, TypeU32(state), indexed, offset);
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}
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} else {
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const uint32_t stride_enum = (packed >> 16u) & 3u;
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const uint32_t index_stride = 8u << stride_enum;
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const auto index_msb = Binary(state, spv::OpShiftRightLogical, TypeU32(state), index,
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ConstantU32(state, stride_enum + 3u));
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const auto index_lsb = Binary(state, spv::OpBitwiseAnd, TypeU32(state), index,
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ConstantU32(state, index_stride - 1u));
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const auto offset_msb =
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BufferAddress CalculateBufferAddress(EmitterState& state, uint32_t index, uint32_t offset,
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uint32_t soffset, uint32_t immediate, uint32_t stride,
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uint32_t swizzle, uint32_t index_stride) {
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if (immediate != 0u) {
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offset = Binary(state, spv::OpIAdd, TypeU32(state), offset, ConstantU32(state, immediate));
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}
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const auto indexed = Binary(state, spv::OpIMul, TypeU32(state), index, stride);
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auto address = Binary(state, spv::OpIAdd, TypeU32(state), indexed, offset);
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if (swizzle != 0u) {
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const auto index_shift =
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Binary(state, spv::OpIAdd, TypeU32(state), index_stride, ConstantU32(state, 3));
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const auto indices = Binary(state, spv::OpShiftLeftLogical, TypeU32(state),
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ConstantU32(state, 1), index_shift);
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const auto index_msb =
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Binary(state, spv::OpShiftRightLogical, TypeU32(state), index, index_shift);
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const auto index_lsb =
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Binary(state, spv::OpBitwiseAnd, TypeU32(state), index,
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Binary(state, spv::OpISub, TypeU32(state), indices, ConstantU32(state, 1)));
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const auto offset_msb =
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Binary(state, spv::OpBitwiseAnd, TypeU32(state), offset, ConstantU32(state, ~3u));
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const auto offset_lsb =
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Binary(state, spv::OpBitwiseAnd, TypeU32(state), offset, ConstantU32(state, 3u));
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const auto indexed_msb = stride == 1u ? index_msb
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: Binary(state, spv::OpIMul, TypeU32(state),
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index_msb, ConstantU32(state, stride));
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const auto msb = Binary(state, spv::OpIMul, TypeU32(state),
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Binary(state, spv::OpIAdd, TypeU32(state), indexed_msb, offset_msb),
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ConstantU32(state, index_stride));
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const auto indexed_msb = Binary(state, spv::OpIMul, TypeU32(state), index_msb, stride);
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const auto msb =
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Binary(state, spv::OpIMul, TypeU32(state),
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Binary(state, spv::OpIAdd, TypeU32(state), indexed_msb, offset_msb), indices);
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const auto lsb = Binary(state, spv::OpIAdd, TypeU32(state),
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Binary(state, spv::OpShiftLeftLogical, TypeU32(state), index_lsb,
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ConstantU32(state, 2u)),
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offset_lsb);
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address = Binary(state, spv::OpIAdd, TypeU32(state), msb, lsb);
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address = Select(state, TypeU32(state), swizzle,
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Binary(state, spv::OpIAdd, TypeU32(state), msb, lsb), address);
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}
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return {offset, Binary(state, spv::OpIAdd, TypeU32(state), address, soffset)};
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}
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const auto soffset_value = inst.Arg(3).Resolve();
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if (soffset_value.IsImmediate() && soffset_value.GetType() == IR::Type::U32 &&
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soffset_value.U32() == 0u) {
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return address;
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uint32_t BufferLane(EmitterState& state) {
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return Binary(state, spv::OpBitwiseAnd, TypeU32(state), EmitSubgroupLocalInvocationId(state),
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ConstantU32(state, 63));
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}
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uint32_t BufferByteAddress(ValueEmitContext& ctx, const IR::Inst& inst, const IR::MemoryInfo& mem) {
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auto& state = ctx.state;
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const auto packed = StorageBufferPackedStride(state, mem);
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const auto stride = packed & 0x3fffu;
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auto index = ctx.Arg(inst, 1);
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if ((packed & (1u << 20u)) != 0u) {
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index = Binary(state, spv::OpIAdd, TypeU32(state), index, BufferLane(state));
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}
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return Binary(state, spv::OpIAdd, TypeU32(state), address, soffset);
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const bool swizzle = stride != 0u && (packed & (1u << 14u)) != 0u;
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return CalculateBufferAddress(state, index, ctx.Arg(inst, 2), ctx.Arg(inst, 3), mem.offset,
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ConstantU32(state, stride),
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swizzle ? ConstantBool(state, true) : 0u,
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ConstantU32(state, (packed >> 16u) & 3u))
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.byte;
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}
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uint32_t AddU64Low(EmitterState& state, uint32_t low, uint32_t high, uint32_t add_low,
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@@ -196,11 +201,8 @@ uint32_t LoadBdaDword(ValueEmitContext& ctx, uint32_t address) {
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});
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}
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uint32_t LoadBda(ValueEmitContext& ctx, const IR::Inst& inst, const IR::MemoryInfo& mem,
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uint32_t bits) {
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auto& state = ctx.state;
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const auto address = GuestAddress(ctx, inst, mem);
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const auto active = ctx.Arg(inst, inst.NumArgs() - 1);
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uint32_t LoadBda(ValueEmitContext& ctx, uint32_t address, uint32_t active, uint32_t bits) {
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auto& state = ctx.state;
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return EmitValueOrZeroIfCondition(state, active, [&]() {
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const auto aligned = Binary(state, spv::OpBitwiseAnd, TypeScalarU64(state), address,
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ConstantDeviceAddress(state, ~uint64_t {3}));
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@@ -236,8 +238,7 @@ uint32_t LoadBda(ValueEmitContext& ctx, const IR::Inst& inst, const IR::MemoryIn
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uint32_t ByteAddress(ValueEmitContext& ctx, const IR::Inst& inst, const IR::MemoryInfo& mem) {
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if (mem.kind == IR::ResourceKind::Buffer) {
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return BufferByteAddress(ctx, inst, mem, ctx.Arg(inst, 1), ctx.Arg(inst, 2),
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ctx.Arg(inst, 3));
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return BufferByteAddress(ctx, inst, mem);
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}
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if (mem.kind == IR::ResourceKind::Lds || mem.kind == IR::ResourceKind::Gds) {
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if (mem.offset == 0u) {
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@@ -734,12 +735,86 @@ void FormattedStore(ValueEmitContext& ctx, const IR::Inst& inst, const IR::Memor
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});
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}
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uint32_t LoadIndirectBuffer(ValueEmitContext& ctx, const IR::Inst& inst, uint32_t components) {
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auto& state = ctx.state;
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const auto& handle = *inst.Arg(0).ResolveInstruction();
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const auto word1 = ctx.Arg(handle, 1);
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const auto records = ctx.Arg(handle, 2);
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const auto word3 = ctx.Arg(handle, 3);
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const auto field = [&](uint32_t word, uint32_t first, uint32_t count) {
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return EmitBitFieldUExtract(state, word, ConstantU32(state, first),
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ConstantU32(state, count));
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};
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const auto nonzero = [&](uint32_t value) {
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return Binary(state, spv::OpINotEqual, TypeBool(state), value, ConstantU32(state, 0));
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};
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const auto has_dword = [&](uint32_t offset, uint32_t size) {
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return AndCondition(
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state,
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Binary(state, spv::OpUGreaterThanEqual, TypeBool(state), size, ConstantU32(state, 4)),
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Binary(state, spv::OpULessThanEqual, TypeBool(state), offset,
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Binary(state, spv::OpISub, TypeU32(state), size, ConstantU32(state, 4))));
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};
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const auto stride = field(word1, 16, 14);
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const auto swizzle = AndCondition(state, nonzero(stride), nonzero(field(word1, 31, 1)));
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const auto index_stride = field(word3, 21, 2);
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const auto add_tid = nonzero(field(word3, 23, 1));
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const auto index =
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Binary(state, spv::OpIAdd, TypeU32(state), ctx.Arg(inst, 1),
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Select(state, TypeU32(state), add_tid, BufferLane(state), ConstantU32(state, 0)));
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const auto soffset = ctx.Arg(inst, 3);
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const auto base = DeviceAddressFromWords(state, ctx.Arg(handle, 0), field(word1, 0, 16));
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const auto valid_format = nonzero(field(word3, 12, 7));
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const auto mode = field(word3, 28, 2);
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const auto index_in_bounds = Binary(state, spv::OpULessThan, TypeBool(state), index, records);
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const auto scalar_in_bounds =
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Binary(state, spv::OpULessThanEqual, TypeBool(state), soffset, records);
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const auto raw_records = Binary(state, spv::OpISub, TypeU32(state), records, soffset);
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const auto raw_index_in_bounds =
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Binary(state, spv::OpULessThan, TypeBool(state), index, raw_records);
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std::array<uint32_t, 4> values {};
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for (uint32_t component = 0; component < components; component++) {
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const auto address = CalculateBufferAddress(state, index, ctx.Arg(inst, 2), soffset,
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ctx.Memory(inst).offset + component * 4u,
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stride, swizzle, index_stride);
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// RDNA2 raw DWORD vectors check each component, unlike formatted accesses.
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const auto structured_bounds =
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AndCondition(state, index_in_bounds,
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Binary(state, spv::OpULessThan, TypeBool(state), address.offset, stride));
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// OOB_SELECT=3 reduces NUM_RECORDS by SOFFSET before the offset/index check.
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const auto raw_bounds = AndCondition(
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state, scalar_in_bounds,
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Select(state, TypeBool(state), swizzle,
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AndCondition(state, raw_index_in_bounds, has_dword(address.offset, stride)),
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has_dword(address.offset, raw_records)));
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auto in_bounds =
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Select(state, TypeBool(state),
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Binary(state, spv::OpIEqual, TypeBool(state), mode, ConstantU32(state, 0)),
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structured_bounds, index_in_bounds);
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in_bounds = Select(
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state, TypeBool(state),
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Binary(state, spv::OpULessThan, TypeBool(state), mode, ConstantU32(state, 2)),
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in_bounds,
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Select(state, TypeBool(state),
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Binary(state, spv::OpIEqual, TypeBool(state), mode, ConstantU32(state, 2)),
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nonzero(records), raw_bounds));
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const auto guest =
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Binary(state, spv::OpIAdd, TypeScalarU64(state), base,
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Unary(state, spv::OpUConvert, TypeScalarU64(state), address.byte));
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values[component] = LoadBda(ctx, guest, AndCondition(state, valid_format, in_bounds), 32u);
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}
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return ConstructU32Composite(state, components, values);
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}
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uint32_t LoadWideBuffer(ValueEmitContext& ctx, const IR::Inst& inst, uint32_t components) {
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auto& state = ctx.state;
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return EmitValueOrDefaultIfCondition(
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state, ctx.Arg(inst, inst.NumArgs() - 1), TypeU32Composite(state, components),
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ConstantU32CompositeZero(state, components), [&]() {
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const auto mem = ctx.Memory(inst);
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if (mem.kind == IR::ResourceKind::IndirectBuffer) {
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return LoadIndirectBuffer(ctx, inst, components);
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}
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const auto resource = PrepareMemoryResourceAccess(state, mem);
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const auto info = Format::GetFormatInfo(
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mem.formatted ? BufferFormat(ctx, mem) : Prospero::BufferFormat::kInvalid);
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@@ -1088,7 +1163,8 @@ void EmitLoadMemory(ValueEmitContext& ctx, const IR::Inst& inst) {
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value = LoadWideShared(ctx, inst, shared_components);
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else if (address_info.access == IR::AddressAccess::Read &&
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mem.kind != IR::ResourceKind::Scratch)
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value = LoadBda(ctx, inst, mem, address_info.data_bits);
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value = LoadBda(ctx, GuestAddress(ctx, inst, mem), ctx.Arg(inst, inst.NumArgs() - 1),
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address_info.data_bits);
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else if (op == IR::ValueOpcode::LoadBufferU32 && mem.formatted)
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value = FormattedLoad(ctx, inst, mem);
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else if (inst.GetType() == IR::Type::U8)
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@@ -447,13 +447,20 @@ void ValidateProgram(const Program& program, bool require_ssa) {
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ValueOpcodeName(inst.GetOpcode())));
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}
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const auto& memory = program.memory_info[memory_index];
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if (memory.kind != ResourceKind::Buffer &&
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memory.kind != ResourceKind::ScalarBuffer) {
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const bool vector_buffer = memory.kind == ResourceKind::Buffer ||
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memory.kind == ResourceKind::IndirectBuffer;
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if (!vector_buffer && memory.kind != ResourceKind::ScalarBuffer) {
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return Fail(fmt::format("{} has a non-buffer resource kind",
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ValueOpcodeName(inst.GetOpcode())));
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}
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if (memory.kind == ResourceKind::IndirectBuffer &&
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(memory.formatted || memory.typed ||
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(inst.GetOpcode() != ValueOpcode::LoadBufferU32x2 &&
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inst.GetOpcode() != ValueOpcode::LoadBufferU32x4))) {
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return Fail("indirect buffer requires a raw DWORD x2/x4 load");
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}
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if (buffer_components > 1u &&
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(memory.kind != ResourceKind::Buffer || memory.data_bits != 32u ||
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(!vector_buffer || memory.data_bits != 32u ||
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memory.data_dwords != buffer_components || memory.component_index != 0u)) {
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return Fail(fmt::format("{} has inconsistent native-wide metadata",
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ValueOpcodeName(inst.GetOpcode())));
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@@ -27,6 +27,7 @@ enum class ResourceKind {
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ScalarBuffer,
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ScalarAddress,
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Buffer,
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IndirectBuffer,
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Flat,
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Global,
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Scratch,
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@@ -526,7 +526,7 @@ private:
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}
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}
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void GetHandle(Value value, ValueOpcode expected, uint32_t width, uint32_t pc, Inst*& handle,
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bool GetHandle(Value value, ValueOpcode expected, uint32_t width, uint32_t pc, Inst*& handle,
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uint32_t& source, bool sampler = false, bool sample_adjust = false) {
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handle = value.Resolve().TryInstruction();
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if (handle == nullptr || handle->GetOpcode() != expected) {
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@@ -546,10 +546,16 @@ private:
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bad_dword = 0;
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}
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if (!ValidateSource(descriptor, bad_dword)) {
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if (expected == ValueOpcode::GetBufferResource &&
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std::all_of(descriptor.dwords.begin(), descriptor.dwords.begin() + width,
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[](Value word) { return word.Resolve().GetType() == Type::U32; })) {
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return false;
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}
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Fail(pc, fmt::format("{} dword {} is not a valid runtime value",
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ValueOpcodeName(expected), bad_dword));
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}
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source = InternSource(descriptor);
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return true;
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}
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void ValidateAddressHandle(Value value, uint32_t pc) const {
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@@ -720,7 +726,18 @@ private:
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uint32_t resource = 0;
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if (buffer != BufferAccess::None) {
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GetHandle(inst.Arg(0), ValueOpcode::GetBufferResource, 4, flags.pc, handle, source);
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if (!GetHandle(inst.Arg(0), ValueOpcode::GetBufferResource, 4, flags.pc, handle,
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source)) {
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if (memory.kind != ResourceKind::Buffer || memory.formatted || memory.typed ||
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(op != ValueOpcode::LoadBufferU32x2 && op != ValueOpcode::LoadBufferU32x4)) {
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Fail(flags.pc,
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"buffer descriptor is not a valid runtime value; GPU-selected access "
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"requires a raw DWORD x2/x4 load");
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}
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m_program.memory_info[flags.index].kind = ResourceKind::IndirectBuffer;
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m_info.uses_dma = true;
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return;
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}
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resource = AddBuffer(source, memory, op, flags.pc);
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if (resource == UINT32_MAX) {
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Fail(flags.pc, "buffer resource limit exceeded");
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@@ -22529,6 +22529,75 @@ TestCase BufferLoadDwordx4ZeroesOnlyOutOfBoundsTail() {
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return test;
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}
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TestCase BufferLoadsGpuSelectedDescriptors() {
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using O = ShaderOpcode;
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constexpr uint64_t GuestBase = 0x0000000110000000ull;
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struct DescriptorCase {
|
||||
u32 stride, records, mode, soffset;
|
||||
bool swizzle, bound;
|
||||
std::array<u32, 6> expected;
|
||||
};
|
||||
const DescriptorCase cases[] = {
|
||||
{24, 2, 0, 0, false, true, {7, 8, 9, 10, 11, 12}},
|
||||
{12, 2, 0, 0, false, true, {4, 5, 6, 0, 0, 0}},
|
||||
{12, 2, 1, 0, false, true, {4, 5, 6, 7, 8, 9}},
|
||||
{12, 1, 2, 0, false, true, {4, 5, 6, 7, 8, 9}},
|
||||
{12, 0, 2, 0, false, true, {}},
|
||||
// OOB3 checks offset + soffset, independently of index * stride.
|
||||
{12, 20, 3, 4, false, true, {5, 6, 7, 8, 0, 0}},
|
||||
{12, 2, 0, 0, false, false, {}},
|
||||
// RDNA2 swizzling uses four-byte elements; soffset is added afterward.
|
||||
{12, 2, 0, 4, true, true, {3, 11, 19, 0, 0, 0}},
|
||||
{12, 8, 3, 4, true, true, {3, 11, 19, 0, 0, 0}},
|
||||
{12, 4, 3, 4, true, true, {}},
|
||||
};
|
||||
TestCase test;
|
||||
test.name = "BufferLoadsGpuSelectedDescriptors";
|
||||
test.initial.resize(2048);
|
||||
for (u32 i = 0; i < std::size(cases); ++i) {
|
||||
const auto &input = cases[i];
|
||||
const u32 data_offset = 4096 + i * 128;
|
||||
// 120-byte table entries with a descriptor at byte 8, as in PPSA04677.
|
||||
const std::array<u32, 4> descriptor{
|
||||
static_cast<u32>(GuestBase + data_offset),
|
||||
(input.stride << 16u) | (input.swizzle ? 1u << 31u : 0u) | 1u,
|
||||
input.records, (input.bound ? 0x5204u : 0x204u) | (input.mode << 28u)};
|
||||
std::copy(descriptor.begin(), descriptor.end(), test.initial.begin() + 130 + i * 30);
|
||||
for (u32 word = 0; word < 32; ++word) {
|
||||
test.initial[data_offset / 4 + word] = i * 100 + word + 1;
|
||||
}
|
||||
// Reverse the table order through a GPU load and readfirstlane, not host constants.
|
||||
const u32 selected = static_cast<u32>(std::size(cases)) - 1 - i;
|
||||
test.initial[64 + i] = selected;
|
||||
AppendVMovU32(&test.code, 30, (64 + i) * 4);
|
||||
AppendBufferLoadDword(&test.code, 0, 30);
|
||||
test.code.push_back(EncodeVop1(0x02, 20, Vgpr(0)));
|
||||
test.code.push_back(EncodeSop2(0x26, 20, 20, 255)); // s_mul_i32 s20, s20, 120
|
||||
test.code.push_back(120);
|
||||
test.code.push_back(EncodeSmem0(0x0a, 8, 0));
|
||||
test.code.push_back(EncodeSmem1(520, 20));
|
||||
AppendSMovLiteral(&test.code, 22, cases[selected].soffset);
|
||||
AppendVMovU32(&test.code, 21, 1);
|
||||
test.code.push_back(EncodeMubuf0(0x0e, 0, true, false));
|
||||
test.code.push_back(EncodeMubuf1(0, 2, 21, 22));
|
||||
test.code.push_back(EncodeMubuf0(0x0d, 16, true, false));
|
||||
test.code.push_back(EncodeMubuf1(4, 2, 21, 22));
|
||||
for (u32 component = 0; component < 6; ++component) {
|
||||
AppendStoreVgpr(&test.code, component, i * 6 + component);
|
||||
const u32 expected = cases[selected].expected[component];
|
||||
test.expected.push_back(expected == 0 ? 0 : selected * 100 + expected);
|
||||
}
|
||||
}
|
||||
AppendEnd(&test.code);
|
||||
test.bda_mappings = {{GuestBase, 0}};
|
||||
test.opcodes = {O::V_MOV_B32, O::S_MOV_B32, O::BUFFER_LOAD_DWORD,
|
||||
O::V_READFIRSTLANE_B32, O::S_MUL_I32, O::S_BUFFER_LOAD_DWORDX4,
|
||||
O::BUFFER_LOAD_DWORDX4, O::BUFFER_LOAD_DWORDX2,
|
||||
O::BUFFER_STORE_DWORD, O::S_ENDPGM};
|
||||
test.required_spirv = {"OpConvertUToPtr", "PhysicalStorageBuffer"};
|
||||
return test;
|
||||
}
|
||||
|
||||
TestCase BufferStoreDwordx4DropsOnlyOutOfBoundsTail() {
|
||||
using O = ShaderOpcode;
|
||||
|
||||
@@ -27572,6 +27641,7 @@ std::vector<TestCase> MakeCases() {
|
||||
AddCase(BufferLoadDwordx3SnapshotsOverlappingAddress);
|
||||
AddCase(BufferLoadDwordx4SnapshotsOverlappingAddress);
|
||||
AddCase(BufferLoadDwordx4ZeroesOnlyOutOfBoundsTail);
|
||||
AddCase(BufferLoadsGpuSelectedDescriptors);
|
||||
AddCase(BufferStoreDwordx4DropsOnlyOutOfBoundsTail);
|
||||
AddCase(BufferLoadFormatXyzwRejectsPartialRecord);
|
||||
AddCase(BufferStoreFormatXyzwDropsPartialRecord);
|
||||
@@ -32298,6 +32368,16 @@ int main(int argc, char **argv) {
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
if (argc == 2 && std::strcmp(argv[1], "--indirect-buffer-only") == 0) {
|
||||
VulkanHarness vulkan;
|
||||
RunCase(&vulkan, BufferLoadsGpuSelectedDescriptors());
|
||||
RunCase(&vulkan, BufferLoadDwordx4SnapshotsOverlappingAddress());
|
||||
RunCase(&vulkan, BufferLoadDwordx4ZeroesOnlyOutOfBoundsTail());
|
||||
RunCase(&vulkan, BufferLoadDwordIdxenUsesDescriptorStride());
|
||||
RunCase(&vulkan, BufferStoreFormatXAddTidUsesLaneIndex());
|
||||
RunCase(&vulkan, FlatVirtualAddressRebasesGuestAllocation());
|
||||
return 0;
|
||||
}
|
||||
if (argc == 2 && std::strcmp(argv[1], "--wave64-only") == 0) {
|
||||
VulkanHarness vulkan;
|
||||
RunCase(&vulkan, Wave32VccMasksPreserveOtherHalf());
|
||||
|
||||
Reference in New Issue
Block a user