5af370c257
shader: add BUFFER_STORE_FORMAT_D16_X opcode
2026-10-07 16:22:30 +04:00
bb98f26433
shader: add missing I64/U64 compare variants
2026-10-07 05:03:09 +04:00
7492cb9577
shader: emulate DS_ORDERED_COUNT as a GDS atomic ( #1117 )
...
* feat(shader): emulate DS_ORDERED_COUNT as a GDS atomic
* fix(shader): issue one ordered-count atomic per wave
* shader: correct ordered-count addressing and wave results
Use the M0 base and pixel packer offset for the GDS counter. Broadcast the
previous value to every lane and preserve the counter when EXEC is empty.
Add GPU regressions for add/exchange with full, partial, and empty EXEC in
wave32 and wave64. The targeted DS and buffer atomic suite passes 63 cases.
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-07 01:45:37 +04:00
1195af2510
decoder: add V_CMPX_U_F32 ( #1120 )
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feat(decoder): add V_CMPX_U_F32
2026-10-07 01:16:23 +04:00
5601861d67
shader: implement RDNA2 scalar 16-bit sign extension
2026-10-06 14:53:17 +04:00
7a0e1dafd7
shader: classify native half values with shared operand decoding
2026-10-05 18:39:31 +04:00
1d55272467
shader: support V_CMPX_NE_U16
2026-10-05 09:25:19 +04:00
2b1b7ed0e4
shader: FLAT opcode=0x24
2026-10-05 08:48:20 +04:00
d8be245c22
shader: separate legacy FP32 MAD rounding from fused FMA
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-05 04:11:48 +04:00
8274e517b2
shader: add FP64 min, max and rounding
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Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
98557a83b6
shader: implement RDNA2 DS masked OR through shared atomic updates
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
c17fa5b936
shader: implement RDNA2 DS forward lane permute
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
b8946fef94
shader: translate RDNA2 signed 64-bit not-equal comparisons
2026-10-04 18:39:34 +04:00
284d58d1d5
shader: implement RDNA2 double-precision fractional part
2026-10-04 18:39:34 +04:00
f58014ff0e
shader: preserve wave-wide vector-store completion before publication
2026-10-04 18:39:34 +04:00
b3e419ff11
shader: implement 32-bit RDNA2 IMAGE_ATOMIC_CMPSWAP ( #952 )
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* shader: implement 32-bit RDNA2 image atomic compare-and-swap
* shader: share atomic emission and correct image barriers
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-02 01:15:53 +04:00
0d0b215fab
shader: port 64-bit ALU and atomic opcodes
2026-10-02 00:51:15 +04:00
337f432016
shader: execute PS5 BVH intersections and local FLAT stacks
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Jean-Philippe <github@meunier.jp >
2026-10-02 00:51:15 +04:00
581dad7dd3
shader: implement RDNA2 FP64 equality comparisons
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Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-02 00:51:15 +04:00
64dcbe0ea1
shader: decode the combined conditional-debug branch
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Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com >
2026-10-02 00:51:15 +04:00
bc193f5272
shader: V_CMPX_LT_I16 + fix SDWA with SEXT
2026-09-30 20:49:20 +04:00
6799ecbc5b
shader: add native 64-bit LDS OR with shared typed storage views
2026-09-29 19:13:33 +04:00
35c4dca2ce
shader: add V_CMPX_NLE_F16 opcode
2026-09-29 19:13:33 +04:00
0a5774be7b
shader: support FP64 conversions used by FighterZ ( #884 )
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shader: support float and unsigned widening to FP64
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-28 17:39:31 +04:00
16b83a034c
Shader: execute RDNA2 FP64 shadow arithmetic and log denorm limits
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Shader: disable FP64 denorm preservation controls for now
2026-09-26 15:15:35 +04:00
cf268af839
Shader: implement RDNA2 image atomic float maximum
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Shader: implement RDNA2 image atomic float minimum
Co-authored-by: foufouadi <attar.foued@gmail.com >
Co-authored-by: frans <francois.att@gmail.com >
Co-authored-by: fxpw <fxpw@outlook.com >
Co-authored-by: Matthew Hurley <171001439+theantipopau@users.noreply.github.com >
2026-09-26 15:15:35 +04:00
ff54608569
shader: add V_CMPX_O_F32 opcode
2026-09-25 14:27:09 +04:00
5a705dd15f
shader: support V_CMPX_EQ_U16 ( #816 )
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* shader: support V_CMPX_EQ_U16
Decode gfx11 VOPC 0xba and lower it as an unsigned 16-bit equality
compare with CMPX EXEC-mask semantics.
🤖 Generated with Codebuff 🤖
Co-Authored-By: Codebuff <noreply@codebuff.com >
* shader: correct CMPX EQ U16 runtime expectations
Remove the added CFG tests and correct two EXEC expectations in the compute regression case.
---------
Co-authored-by: Matthew Hurley <171001439+theantipopau@users.noreply.github.com >
Co-authored-by: Codebuff <noreply@codebuff.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-25 02:27:44 +04:00
d72a79af2d
graphics: skip compute dispatches with BVH instructions
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Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
dc9280d75d
shader: add GLC/DLC buffer cache policy support
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Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
e43c242683
shader: add S_MEMREALTIME opcode
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Co-authored-by: Maxime Allanic <maxime@allanic.me >
Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
3dc3fd0197
shader: implement DS_INC_U32 and DS_DEC_U32 ( #790 )
2026-09-24 00:45:12 +04:00
fc86509aac
shader: support DS_WRITE_B8_D16_HI ( #794 )
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Decode GFX10 DS opcode 0xa0 as DS_WRITE_B8_D16_HI (next to
DS_WRITE_B16_D16_HI at 0xa1) and lower it through the existing 8-bit
shared-memory write. The stored byte is bits 23:16 of the data VGPR,
selected with SDWA BYTE_2 on src1.
Add captured-instruction decode coverage (from GTA V, PPSA04264) and a
runtime regression that writes one byte of a distinctive source value
into a pre-filled LDS dword.
2026-09-24 00:44:39 +04:00
549495575c
shader: add S_BITCMP0_B64 and S_BITCMP1_B64 ( #688 )
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* shader: add S_BITCMP0_B64 and S_BITCMP1_B64
* test: move S_BITCMP_B64 coverage to compute suite
* test: use the existing compute CTest entry for bit comparisons
* test: remove the dedicated S_BITCMP_B64 command-line selector
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-20 19:36:12 +04:00
ea6aae8577
shader: V_MAD_I16
2026-09-19 04:43:48 +04:00
5b7d3343cf
shader: V_CMP_NLT_F16
2026-09-18 12:25:13 +04:00
394e638905
shader: V_MUL_LO_U16
2026-09-18 11:21:57 +04:00
bfc8cd0e0b
shader: DPP8 moves
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Co-authored-by: foufouadi <attar.foued@gmail.com >
Co-authored-by: fxpw <fxpw@outlook.com >
2026-09-18 09:11:55 +04:00
cc8e02380f
remove magic_enum wrappers
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Co-authored-by: Saadi <cosxmos@gmail.com >
2026-09-17 20:35:36 +04:00
4b77686566
shader: V_CMP_NGT_F16
2026-09-17 16:56:32 +04:00
f30afc184e
shader: support S_ASHR_I64 ( #658 )
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* shader: implement S_ASHR_I64 with compute coverage
* tests: use existing compute suite for S_ASHR_I64
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-17 10:48:05 +04:00
e0ecffed70
Approximate explicit-LOD texture gathers at mip zero
...
Credits:
YuhiAida (@YuhiAida):
https://github.com/KytyPS5/KytyPS5/pull/588
https://github.com/KytyPS5/KytyPS5/pull/589
https://github.com/KytyPS5/KytyPS5/pull/655
frans (@francoisatt):
https://github.com/KytyPS5/KytyPS5/pull/590
BlackCAT (@psnwd):
https://github.com/KytyPS5/KytyPS5/pull/613
shadowbeat070 (@shadowbeat070):
https://github.com/KytyPS5/KytyPS5/pull/654
Pouare514 (@Pouare514):
https://github.com/KytyPS5/KytyPS5/pull/29
https://github.com/KytyPS5/KytyPS5/pull/32
2026-09-17 08:39:57 +04:00
5b541375a3
shader: implement S_CBRANCH_CDBGSYS opcode
2026-09-16 17:04:48 +04:00
87971a28f5
gpu: isolate tessellation analysis and SPIR-V emission
2026-09-14 06:58:32 +04:00
a21ffde34e
shader: decode and translate V_FRACT_F16 (VOP1 0x5f) and V_CMPX_LT_U16 (VOPC 0xb9) ( #582 )
...
shader: support V_FRACT_F16 and V_CMPX_LT_U16
Decode compact, SDWA, and VOP3 forms using the existing arithmetic and comparison paths. Preserve EXEC masking and VCC for the integer compare, and reject unsupported DPP encoding.
Add captured-instruction, operand-selection, floating-point edge, and execution-mask regression coverage.
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-12 17:21:32 +04:00
7bcd43dbee
shader: support S_MUL_HI_I32 (SOP2 0x36) ( #576 )
2026-09-12 14:56:14 +04:00
c3546577b6
shader: implement S_WQM_B32
...
Co-authored-by: Brandon Strong <brandostrong@gmail.com >
2026-09-10 14:11:46 +04:00
c913951f7b
shader: implement RDNA2 subvector loop mask and branch semantics
2026-09-10 14:11:46 +04:00
3902b42096
shader: share direct and conditional branch classification
2026-09-10 14:11:46 +04:00
32ea0869e5
shader: implement S_ORN2_SAVEEXEC_B32
2026-09-09 13:11:48 +04:00
nmzik