763d3be3a9
graphics: add opt-in ZMask support and launcher rendering options
2026-10-17 17:50:02 +02:00
d8c4a9af38
graphics: preserve HTILE metadata across native image replacement
2026-10-17 17:31:25 +02:00
9f88043ebe
shader: use compact integer RTZ half conversion
2026-10-17 12:23:12 +02:00
5bf37f52ad
renderer: clear compressed stencil with pending depth metadata
2026-10-17 09:50:11 +02:00
57791645e4
renderer: track attachment load clears by image aspect
2026-10-17 09:34:51 +02:00
d1fe1324c8
shader: keep coherent 64bit atomic
2026-10-17 07:52:20 +02:00
b82512be06
shader: read float inline constants on 64-bit operands as f64 bits ( #1576 )
...
A float inline constant (240-248) read by a 64-bit operand is the f64 bit
pattern for integer B64 opcodes too: AMD's compilers emit
v_lshrrev_b64 v[4:5], v0, 1.0 for 0x3ff0000000000000 >> lane. ReadU32Pair
returned {f32 bits, 0}, so only F64-typed reads had the right value.
Based on TheCruZ's 284deab28 (closed #1219 ).
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
2026-10-17 05:21:06 +02:00
ba8b0c85b8
shader: keep quiet NaNs with payload bits out of the packed f16 min/max sNaN path ( #1579 )
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V_PK_MIN_F16 and V_PK_MAX_F16 return the quieted NaN for a signaling NaN
operand and the other operand for a quiet one (per half, as V_MIN_F16 and
V_MAX_F16 do). The signaling test masked the half with 0x7c00 and checked
for a nonzero payload, so a quiet NaN with payload bits such as 0x7e01 was
taken as signaling and returned. Mask with 0x7e00 so the quiet bit must be
clear.
Two more vectors in PackedMinMaxF16NanAndSignedZeroEdges cover it.
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
2026-10-17 05:12:37 +02:00
e93b4b0378
shader: support returning 32-bit LDS compare-exchange (DS_CMPST_RTN_B32) ( #1578 )
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* shader: support DS_CMPST_RTN_B32
Assassin's Creed Valhalla (PPSA01490, #281 ) stops on DS opcode 0x30 in a
compute shader. DS compares DATA and stores DATA2, the opposite of
BUFFER_ATOMIC_CMPSWAP, so the 32-bit atomic path swaps the two for this
opcode, as the 64-bit form does.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: reject unsupported GDS compare-store variant
---------
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-17 04:37:16 +02:00
9202bddad2
recognize verified pattern fills
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Co-authored-by: Juan Pablo Farias <juanpablo.profissional.a.f@gmail.com >
2026-10-17 04:09:54 +02:00
02ead0e2e1
shader: 64-bit buffer atomic add (BUFFER_ATOMIC_ADD_X2)
2026-10-17 04:09:54 +02:00
4f1f3b1bb3
shader: make the f32 clamp modifier turn NaN into 0
2026-10-17 04:09:53 +02:00
d01633e18e
Revert "Fix scalar buffer reads across sparse guest mappings"
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This reverts commit d7974dc763
2026-10-16 19:13:36 +02:00
d7974dc763
Fix scalar buffer reads across sparse guest mappings
2026-10-16 18:20:31 +02:00
d58aefde49
renderer: reduce synchronization and allocation overhead
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Performance changes from #1495 :
- Sync changed BDA ranges instead of scanning all mappings.
- Let VMA suballocate BDA buffers.
- Remove the renderer lock from presentation.
- Keep compatible pipeline caches across builds.
- Fold masked shifts that always produce zero.
2026-10-16 17:18:49 +02:00
57b161019d
shader: honor front-face input format
2026-10-16 12:57:27 +02:00
13e4c315b6
agc: Cleanup names so they match NIDs ( #1508 )
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* agc: Cleanup names so they match NIDs
Simple commit tidying up libSceAgc function names so they match their
NIDs. This just a tidy-up commit that makes it more obvious what each
function is.
* agc: Preserve unknown fused shader size name
2026-10-16 02:16:19 +02:00
c6b8210d7c
test: fix the Linux and Windows CI test builds ( #1504 )
2026-10-16 01:43:24 +02:00
a5ceb48184
agc: encode acquire-memory byte ranges in standard packets
2026-10-15 23:34:42 +02:00
f7226ca7dc
graphics: emit PS5 register object and primitive IDs to RT7
2026-10-15 22:28:01 +02:00
2caf2f7e4e
shader: retain runtime count bounds for finite descriptor choices
2026-10-15 22:28:01 +02:00
e291589177
shader: resolve GPU-selected parent pointers and bounded child image tables
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
2285a25182
shader: prove narrowing loop masks through shared implication analysis
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
a50e4de389
shader: recognize reversed unsigned greater-than resource bounds
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
232e2f2593
shader: bound waterfall buffer descriptors with same-lane guards
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
b4406b0467
graphics: render packed 11-11-10 UNorm targets with exact rounding
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
2a4ccaa5d5
shader: share proven selector domains for paired images and samplers
2026-10-15 22:28:01 +02:00
5916a184cc
shader: preserve affine image heap candidate domains
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
81169d77ea
shader: materialize compact image and paired sampler tables
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
1d3fd07fe6
shader: share indirect buffer format geometry lookup
2026-10-15 22:28:01 +02:00
279bc95941
graphics: track HTile clears across PS5 depth array slices
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
bb2d6dbeb3
shader: share scalar condition results with direct subgroup votes
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
c1f6838e40
shader: share repeated raw indirect buffer load bodies
2026-10-15 22:28:01 +02:00
6455546f26
shader: admit bounded multi-component formatted buffer loads
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:00 +02:00
dcc642551f
graphics: classify signed byte textures for native sampling
2026-10-15 22:28:00 +02:00
dd429ef858
shader: decode high-half formatted buffer stores
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:00 +02:00
bc2664cefa
shader: decode comparison gathers with explicit LOD
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:00 +02:00
8b81f665a2
shader: separate indirect buffer candidates from tracked root limits
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 21:19:38 +02:00
1039c54f5d
shader: share indirect buffer array access after an empty root
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 21:17:44 +02:00
2f6ee0e91d
shader: support RDNA2 high-half short buffer stores
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 20:55:50 +02:00
166b9a5eea
test: dispatch null texture coverage with the intended wave size
2026-10-14 20:47:25 +02:00
5313181ecf
shader: bound workgroup selector prefixes from runtime starting indices
2026-10-14 20:39:25 +02:00
ceccd746d8
shader: resolve workgroup-selected descriptor prefixes from dispatch arguments
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 20:29:48 +02:00
4843d8d942
shader: support packed D16 XYZW formatted buffer stores
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 19:35:08 +02:00
c914435f20
shader: plan finite GPU-selected RGBA16 buffer stores
2026-10-14 19:13:16 +02:00
b6da068313
shader: preserve typed candidates for unfiltered indirect image access
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 18:57:26 +02:00
127cf8d46f
shader: route image stores through shared indirect descriptor access
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 18:39:40 +02:00
e0586cc85a
shader: decode unsigned byte loads into preserved low halves
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 18:21:58 +02:00
302240da70
shader: lower complete wave minima for sparse fragment subgroups
2026-10-14 18:03:48 +02:00
892e70c8a1
graphics: bind unbound textures as native null descriptors
2026-10-14 17:56:47 +02:00
nmzik