Commit Graph

563 Commits

Author SHA1 Message Date
nmzik 9f88043ebe shader: use compact integer RTZ half conversion 2026-10-17 12:23:12 +02:00
nmzik c2173801d4 shader: skip resources in proven empty unsigned loops 2026-10-17 10:38:14 +02:00
nmzik d1fe1324c8 shader: keep coherent 64bit atomic 2026-10-17 07:52:20 +02:00
nmzik ec08ea197b shader: new fill pattern 2026-10-17 06:24:29 +02:00
nmzik f6f1ac8b40 shader: batch dependent folds to avoid repeated SSA graph walks 2026-10-17 06:20:02 +02:00
Nawid3333 b82512be06 shader: read float inline constants on 64-bit operands as f64 bits (#1576)
A float inline constant (240-248) read by a 64-bit operand is the f64 bit
pattern for integer B64 opcodes too: AMD's compilers emit
v_lshrrev_b64 v[4:5], v0, 1.0 for 0x3ff0000000000000 >> lane. ReadU32Pair
returned {f32 bits, 0}, so only F64-typed reads had the right value.

Based on TheCruZ's 284deab28 (closed #1219).

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-17 05:21:06 +02:00
Nawid3333 ba8b0c85b8 shader: keep quiet NaNs with payload bits out of the packed f16 min/max sNaN path (#1579)
V_PK_MIN_F16 and V_PK_MAX_F16 return the quieted NaN for a signaling NaN
operand and the other operand for a quiet one (per half, as V_MIN_F16 and
V_MAX_F16 do). The signaling test masked the half with 0x7c00 and checked
for a nonzero payload, so a quiet NaN with payload bits such as 0x7e01 was
taken as signaling and returned. Mask with 0x7e00 so the quiet bit must be
clear.

Two more vectors in PackedMinMaxF16NanAndSignedZeroEdges cover it.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-17 05:12:37 +02:00
Nawid3333 b6bd9ecae4 shader: read float inline constants on 16-bit operands as half bits (#1582)
The 16-bit encodings of the float inline constants are fixed: the exact
halves of 0.5, 1.0, 2.0 and 4.0 and their negations, and 0x3118 for
1/(2*pi). Read16LaneBits converted the 32-bit value at run time instead,
through PackHalf2x16, which the AMD driver rounds toward zero, so
1/(2*pi) became 0x3117. Use the encodings directly.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-17 05:05:40 +02:00
Nawid3333 e93b4b0378 shader: support returning 32-bit LDS compare-exchange (DS_CMPST_RTN_B32) (#1578)
* shader: support DS_CMPST_RTN_B32

Assassin's Creed Valhalla (PPSA01490, #281) stops on DS opcode 0x30 in a
compute shader. DS compares DATA and stores DATA2, the opposite of
BUFFER_ATOMIC_CMPSWAP, so the 32-bit atomic path swaps the two for this
opcode, as the 64-bit form does.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* shader: reject unsupported GDS compare-store variant

---------

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Co-authored-by: nmzik <Nmzik@mail.ru>
2026-10-17 04:37:16 +02:00
nmzik 9202bddad2 recognize verified pattern fills
Co-authored-by: Juan Pablo Farias <juanpablo.profissional.a.f@gmail.com>
2026-10-17 04:09:54 +02:00
Çağatay Güçlü 02ead0e2e1 shader: 64-bit buffer atomic add (BUFFER_ATOMIC_ADD_X2) 2026-10-17 04:09:54 +02:00
NeySlim 4f1f3b1bb3 shader: make the f32 clamp modifier turn NaN into 0 2026-10-17 04:09:53 +02:00
nmzik d01633e18e Revert "Fix scalar buffer reads across sparse guest mappings"
This reverts commit d7974dc763.
2026-10-16 19:13:36 +02:00
nmzik d7974dc763 Fix scalar buffer reads across sparse guest mappings 2026-10-16 18:20:31 +02:00
shadowbeat070 d58aefde49 renderer: reduce synchronization and allocation overhead
Performance changes from #1495:

- Sync changed BDA ranges instead of scanning all mappings.
- Let VMA suballocate BDA buffers.
- Remove the renderer lock from presentation.
- Keep compatible pipeline caches across builds.
- Fold masked shifts that always produce zero.
2026-10-16 17:18:49 +02:00
shadowbeat070 57b161019d shader: honor front-face input format 2026-10-16 12:57:27 +02:00
AN0DIN 83db2efec3 shader: pack v_cvt_pkrtz_f16_f32 with the native half conversion (GTA V) (#1520)
* shader: pack v_cvt_pkrtz_f16_f32 with the native half conversion

The round-toward-zero pack was emulated with integer operations: about 20 to 30 operations
per half. GTA V uses it in 613 of its 656 pixel shaders, about 16 times in each G-buffer
pixel shader.

The pair is now packed with PackHalf2x16, unpacked again, and each half whose magnitude
exceeds its input's takes one unit off. Half signs and magnitudes are separate, so that is
the next value toward zero, whatever rounding the native conversion uses as long as it
returns one of the two neighbours. Same bits as before for every finite input and infinity;
a NaN stays a NaN. Checked against the old code on 2 million values on the CPU, and on an
Apple M5 GPU through Metal (400 000 values, subnormals included, safe and fast math).

GTA V on an Apple M5 (MoltenVK), 1080p, fixed script camera, three places, A B B A between
launches: -1.7 to -2.8 ms per frame (+4 to +6 %).

Scope: generic
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* shader: remove half-pack commentary and unused shift helper

---------

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Co-authored-by: nmzik <Nmzik@mail.ru>
2026-10-16 02:56:35 +02:00
nmzik c8caa27936 shader: preserve folded native constants for descriptor provenance 2026-10-15 23:22:30 +02:00
nmzik f7226ca7dc graphics: emit PS5 register object and primitive IDs to RT7 2026-10-15 22:28:01 +02:00
nmzik d172ab75ca shader: reuse selector domains proven by prior resource accesses 2026-10-15 22:28:01 +02:00
nmzik bcf13e101e shader: validate texture mip ranges and channel selectors 2026-10-15 22:28:01 +02:00
nmzik 2caf2f7e4e shader: retain runtime count bounds for finite descriptor choices 2026-10-15 22:28:01 +02:00
nmzik df92a08990 shader: report descriptor materialization rejection context 2026-10-15 22:28:01 +02:00
nmzik e291589177 shader: resolve GPU-selected parent pointers and bounded child image tables
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik 2285a25182 shader: prove narrowing loop masks through shared implication analysis
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik a50e4de389 shader: recognize reversed unsigned greater-than resource bounds
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik 232e2f2593 shader: bound waterfall buffer descriptors with same-lane guards
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik b4406b0467 graphics: render packed 11-11-10 UNorm targets with exact rounding
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik fb213e8ae5 shader: share packed color component encoding 2026-10-15 22:28:01 +02:00
nmzik 2a4ccaa5d5 shader: share proven selector domains for paired images and samplers 2026-10-15 22:28:01 +02:00
nmzik 9c04abacc5 shader: resolve shared selector keys once per materialization
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik 5916a184cc shader: preserve affine image heap candidate domains
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik fcab4e5d0d shader: trace unsupported sampled image candidate provenance 2026-10-15 22:28:01 +02:00
nmzik fe23334ff0 shader: remove unreachable candidate diagnostic branches 2026-10-15 22:28:01 +02:00
nmzik 81169d77ea shader: materialize compact image and paired sampler tables
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik 7d24972b8f shader: report rejected indirect buffer candidate context 2026-10-15 22:28:01 +02:00
nmzik 1d3fd07fe6 shader: share indirect buffer format geometry lookup 2026-10-15 22:28:01 +02:00
nmzik 65a6f30f51 shader: compare real nested descriptor pointer instructions 2026-10-15 22:28:01 +02:00
nmzik bb2d6dbeb3 shader: share scalar condition results with direct subgroup votes
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik 50844badbf shader: map debug SPIR-V blocks to native RDNA2 PCs 2026-10-15 22:28:01 +02:00
nmzik c1f6838e40 shader: share repeated raw indirect buffer load bodies 2026-10-15 22:28:01 +02:00
nmzik 6455546f26 shader: admit bounded multi-component formatted buffer loads
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:00 +02:00
nmzik dd429ef858 shader: decode high-half formatted buffer stores
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:00 +02:00
nmzik bc2664cefa shader: decode comparison gathers with explicit LOD
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:00 +02:00
nmzik 8b81f665a2 shader: separate indirect buffer candidates from tracked root limits
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 21:19:38 +02:00
nmzik 1039c54f5d shader: share indirect buffer array access after an empty root
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 21:17:44 +02:00
nmzik b24ce3440d shader: track buffer liveness and offsets by resource count
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 21:11:14 +02:00
nmzik 2f6ee0e91d shader: support RDNA2 high-half short buffer stores
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 20:55:50 +02:00
nmzik 5313181ecf shader: bound workgroup selector prefixes from runtime starting indices 2026-10-14 20:39:25 +02:00
nmzik ceccd746d8 shader: resolve workgroup-selected descriptor prefixes from dispatch arguments
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 20:29:48 +02:00