mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 10:56:58 +02:00
nmzik
244 lines
12 KiB
C++
244 lines
12 KiB
C++
#include "graphics/shader/recompiler/frontend/translate/Translator.h"
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#include <array>
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#include <utility>
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namespace Libs::Graphics::ShaderRecompiler::Frontend::Detail {
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bool Translator::TranslatePackedFloat16(const IR::Instruction& inst) {
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IR::ValueOpcode opcode;
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switch (inst.op) {
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case IR::Opcode::PackedAddF16: opcode = IR::ValueOpcode::FPAdd32; break;
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case IR::Opcode::PackedMulF16: opcode = IR::ValueOpcode::FPMul32; break;
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case IR::Opcode::PackedMinF16: opcode = IR::ValueOpcode::FPMin32; break;
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case IR::Opcode::PackedMaxF16: opcode = IR::ValueOpcode::FPMax32; break;
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case IR::Opcode::PackedFmaF16: opcode = IR::ValueOpcode::FPFma32; break;
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default: return false;
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}
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const auto translate_lane = [&](bool high) {
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const auto lhs = ReadF16LaneAsF32(inst.src[0], high, true);
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const auto rhs = ReadF16LaneAsF32(inst.src[1], high, true);
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IR::F32 result;
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if (inst.src_count == 3u) {
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result = IR::F32(
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ir.Emit(opcode, {lhs, rhs, ReadF16LaneAsF32(inst.src[2], high, true)}));
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} else {
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result = IR::F32(ir.Emit(opcode, {lhs, rhs}));
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}
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return ApplyF32ResultModifiers(inst.dst, result);
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};
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auto raw = inst.dst;
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raw.omod = 0u;
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raw.clamp = false;
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auto result = PackHalf2x16(translate_lane(false), translate_lane(true));
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if (inst.op == IR::Opcode::PackedMinF16 || inst.op == IR::Opcode::PackedMaxF16) {
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const auto quiet_snan = [&](const IR::Operand& operand, bool high) {
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const auto bits = ReadU16LaneAsU32(operand, high, false);
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const auto exponent = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x7c00u)));
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const auto payload = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x01ffu)));
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const auto snan = ir.LogicalAnd(ir.IEqual(exponent, IR::U32(IR::Value(0x7c00u))),
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ir.INotEqual(payload, IR::U32(IR::Value(0u))));
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return std::pair {snan, ir.BitwiseOr(bits, IR::U32(IR::Value(0x0200u)))};
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};
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const auto override_lane = [&](bool high) {
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const auto [lhs_snan, lhs_quiet] = quiet_snan(inst.src[0], high);
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const auto [rhs_snan, rhs_quiet] = quiet_snan(inst.src[1], high);
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const auto normal = high ? ir.ShiftRightLogical(result, IR::U32(IR::Value(16u)))
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: ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu)));
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return ir.Select(lhs_snan, lhs_quiet, ir.Select(rhs_snan, rhs_quiet, normal));
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};
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result = PackU16Lanes(override_lane(false), override_lane(true));
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}
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WriteOperand(raw, result);
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return true;
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}
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bool Translator::TranslateFloat16Operation(const IR::Instruction& inst) {
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IR::ValueOpcode opcode;
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switch (inst.op) {
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case IR::Opcode::AddF16: opcode = IR::ValueOpcode::FPAdd32; break;
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case IR::Opcode::SubF16: opcode = IR::ValueOpcode::FPSub32; break;
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case IR::Opcode::MulF16: opcode = IR::ValueOpcode::FPMul32; break;
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case IR::Opcode::MinF16: opcode = IR::ValueOpcode::FPMin32; break;
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case IR::Opcode::MaxF16: opcode = IR::ValueOpcode::FPMax32; break;
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case IR::Opcode::FmaF16:
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case IR::Opcode::MadMixF16: opcode = IR::ValueOpcode::FPFma32; break;
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case IR::Opcode::RcpF16: opcode = IR::ValueOpcode::FPRecip32; break;
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case IR::Opcode::SqrtF16: opcode = IR::ValueOpcode::FPSqrt; break;
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case IR::Opcode::InverseSqrtF16: opcode = IR::ValueOpcode::FPRecipSqrt32; break;
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case IR::Opcode::Log2F16: opcode = IR::ValueOpcode::FPLog2; break;
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case IR::Opcode::Exp2F16: opcode = IR::ValueOpcode::FPExp2; break;
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case IR::Opcode::FloorF16: opcode = IR::ValueOpcode::FPFloor32; break;
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case IR::Opcode::CeilF16: opcode = IR::ValueOpcode::FPCeil32; break;
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case IR::Opcode::TruncF16: opcode = IR::ValueOpcode::FPTrunc32; break;
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case IR::Opcode::RoundEvenF16: opcode = IR::ValueOpcode::FPRoundEven32; break;
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case IR::Opcode::Min3F16: opcode = IR::ValueOpcode::FPMinTri32; break;
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case IR::Opcode::Max3F16: opcode = IR::ValueOpcode::FPMaxTri32; break;
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case IR::Opcode::Med3F16: opcode = IR::ValueOpcode::FPMedTri32; break;
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default: return false;
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}
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < inst.src_count; index++) {
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args[index] = inst.op == IR::Opcode::MadMixF16 ? IR::Value(ReadMixF32(inst.src[index]))
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: IR::Value(ReadF16AsF32(inst.src[index]));
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}
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IR::F32 result;
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switch (inst.src_count) {
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case 1: result = IR::F32(ir.Emit(opcode, {args[0]})); break;
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case 2: result = IR::F32(ir.Emit(opcode, {args[0], args[1]})); break;
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case 3: result = IR::F32(ir.Emit(opcode, {args[0], args[1], args[2]})); break;
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default: EXIT("invalid half-float source count: %u", inst.src_count);
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}
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if (inst.op == IR::Opcode::SqrtF16 || inst.op == IR::Opcode::InverseSqrtF16 ||
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inst.op == IR::Opcode::Log2F16) {
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const auto negative = IR::U1(
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ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {args[0], IR::Value::F32(0.0f)}));
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result = ApplyF32ResultModifiers(inst.dst, result);
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const auto bits = PackHalf2x16(result, IR::F32(IR::Value::F32(0.0f)));
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const auto invalid = IR::U32(IR::Value(inst.dst.clamp ? 0u : 0xfe00u));
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WriteU16(inst.dst, ir.Select(negative, invalid, bits));
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return true;
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}
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WriteF16(inst.dst, result);
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return true;
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}
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bool Translator::TranslateFloatOperation(const IR::Instruction& inst) {
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if (inst.op == IR::Opcode::FrexpMantF32) {
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const auto bits = ReadU32(inst.src[0]);
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const auto exponent = IR::U32(
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ir.Emit(IR::ValueOpcode::BitFieldUExtract, {bits, IR::Value(23u), IR::Value(8u)}));
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const auto mantissa = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x007fffffu)));
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const auto sign = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x80000000u)));
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const auto base = ir.BitwiseOr(sign, IR::U32(IR::Value(0x3f000000u)));
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const auto normal = ir.BitwiseOr(base, mantissa);
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const auto msb = IR::U32(ir.Emit(IR::ValueOpcode::FindUMsb32, {mantissa}));
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const auto shift = ir.ISub(IR::U32(IR::Value(23u)), msb);
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const auto fraction =
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ir.BitwiseAnd(ir.ShiftLeftLogical(mantissa, shift), IR::U32(IR::Value(0x007fffffu)));
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const auto subnormal = ir.BitwiseOr(base, fraction);
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const auto zero = ir.IEqual(mantissa, IR::U32(IR::Value(0u)));
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const auto finite = ir.Select(ir.INotEqual(exponent, IR::U32(IR::Value(0u))), normal,
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ir.Select(zero, bits, subnormal));
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const auto result = ir.Select(ir.IEqual(exponent, IR::U32(IR::Value(0xffu))), bits, finite);
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WriteOperand(inst.dst, ir.BitCastF32(result));
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return true;
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}
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IR::ValueOpcode opcode {};
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switch (inst.op) {
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case IR::Opcode::RcpF32: opcode = IR::ValueOpcode::FPRecip32; break;
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case IR::Opcode::RcpIflagF32: opcode = IR::ValueOpcode::FPRecipIFlag32; break;
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case IR::Opcode::FractF32: opcode = IR::ValueOpcode::FPFract32; break;
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case IR::Opcode::TruncF32: opcode = IR::ValueOpcode::FPTrunc32; break;
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case IR::Opcode::CeilF32: opcode = IR::ValueOpcode::FPCeil32; break;
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case IR::Opcode::RoundEvenF32: opcode = IR::ValueOpcode::FPRoundEven32; break;
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case IR::Opcode::FloorF32: opcode = IR::ValueOpcode::FPFloor32; break;
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case IR::Opcode::Exp2F32: opcode = IR::ValueOpcode::FPExp2; break;
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case IR::Opcode::Log2F32: opcode = IR::ValueOpcode::FPLog2; break;
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case IR::Opcode::InverseSqrtF32: opcode = IR::ValueOpcode::FPRecipSqrt32; break;
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case IR::Opcode::SqrtF32: opcode = IR::ValueOpcode::FPSqrt; break;
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case IR::Opcode::SinF32: opcode = IR::ValueOpcode::FPSin; break;
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case IR::Opcode::CosF32: opcode = IR::ValueOpcode::FPCos; break;
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case IR::Opcode::FAddF32: opcode = IR::ValueOpcode::FPAdd32; break;
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case IR::Opcode::FSubF32: opcode = IR::ValueOpcode::FPSub32; break;
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case IR::Opcode::FMulF32: opcode = IR::ValueOpcode::FPMul32; break;
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case IR::Opcode::FMinF32: opcode = IR::ValueOpcode::FPMin32; break;
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case IR::Opcode::FMaxF32: opcode = IR::ValueOpcode::FPMax32; break;
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case IR::Opcode::FMadF32: opcode = IR::ValueOpcode::FPFma32; break;
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case IR::Opcode::FMin3F32: opcode = IR::ValueOpcode::FPMinTri32; break;
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case IR::Opcode::FMax3F32: opcode = IR::ValueOpcode::FPMaxTri32; break;
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case IR::Opcode::FMed3F32: opcode = IR::ValueOpcode::FPMedTri32; break;
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case IR::Opcode::LdexpF32: opcode = IR::ValueOpcode::FPLdexp; break;
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default: break;
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}
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if (opcode != IR::ValueOpcode {}) {
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < inst.src_count; index++) {
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const auto arg_type = IR::ArgTypeOf(opcode, index);
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args[index] =
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arg_type == IR::Type::F32
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? (inst.op == IR::Opcode::FMadF32 ? IR::Value(ReadMixF32(inst.src[index]))
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: ReadOperand(inst.src[index], IR::Type::F32))
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: ReadOperand(inst.src[index], arg_type);
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}
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IR::Value result;
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switch (inst.src_count) {
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case 1: result = ir.Emit(opcode, {args[0]}); break;
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case 2: result = ir.Emit(opcode, {args[0], args[1]}); break;
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case 3: result = ir.Emit(opcode, {args[0], args[1], args[2]}); break;
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default: EXIT("invalid floating-point source count: %u", inst.src_count);
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}
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WriteOperand(inst.dst, result);
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return true;
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}
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const auto select_f32 = [&](IR::U1 condition, IR::F32 true_value, IR::F32 false_value) {
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return IR::F32(ir.Emit(IR::ValueOpcode::SelectF32, {condition, true_value, false_value}));
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};
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if (inst.op == IR::Opcode::Dot2AccF32F16) {
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auto a = inst.src[0];
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a.op_sel = false;
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a.op_sel_hi = true;
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auto b = inst.src[1];
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b.op_sel = false;
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b.op_sel_hi = true;
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const auto a_lo = ReadF16LaneAsF32(a, false);
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const auto a_hi = ReadF16LaneAsF32(a, true);
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const auto b_lo = ReadF16LaneAsF32(b, false);
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const auto b_hi = ReadF16LaneAsF32(b, true);
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const auto acc = ReadMixF32(inst.src[2]);
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const auto lo = IR::F32(ir.Emit(IR::ValueOpcode::FPFma32, {a_lo, b_lo, acc}));
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WriteOperand(inst.dst, ir.Emit(IR::ValueOpcode::FPFma32, {a_hi, b_hi, lo}));
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return true;
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}
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if (inst.op != IR::Opcode::CubeIdF32 && inst.op != IR::Opcode::CubeScF32 &&
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inst.op != IR::Opcode::CubeTcF32 && inst.op != IR::Opcode::CubeMaF32) {
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return false;
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}
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const auto x = ReadMixF32(inst.src[0]);
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const auto y = ReadMixF32(inst.src[1]);
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const auto z = ReadMixF32(inst.src[2]);
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const auto nx = IR::F32(ir.Emit(IR::ValueOpcode::FPNeg32, {x}));
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const auto ny = IR::F32(ir.Emit(IR::ValueOpcode::FPNeg32, {y}));
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const auto nz = IR::F32(ir.Emit(IR::ValueOpcode::FPNeg32, {z}));
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const auto ax = IR::F32(ir.Emit(IR::ValueOpcode::FPAbs32, {x}));
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const auto ay = IR::F32(ir.Emit(IR::ValueOpcode::FPAbs32, {y}));
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const auto az = IR::F32(ir.Emit(IR::ValueOpcode::FPAbs32, {z}));
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const auto z_face =
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ir.LogicalAnd(IR::U1(ir.Emit(IR::ValueOpcode::FPOrdGreaterThanEqual32, {az, ax})),
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IR::U1(ir.Emit(IR::ValueOpcode::FPOrdGreaterThanEqual32, {az, ay})));
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const auto y_face = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdGreaterThanEqual32, {ay, ax}));
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const auto x_neg = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {x, IR::Value::F32(0.0f)}));
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const auto y_neg = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {y, IR::Value::F32(0.0f)}));
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const auto z_neg = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {z, IR::Value::F32(0.0f)}));
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const auto select_face = [&](IR::F32 x_value, IR::F32 y_value, IR::F32 z_value) {
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return select_f32(z_face, z_value, select_f32(y_face, y_value, x_value));
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};
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IR::F32 result;
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switch (inst.op) {
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case IR::Opcode::CubeIdF32:
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result = select_face(
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select_f32(x_neg, IR::F32(IR::Value::F32(1.0f)), IR::F32(IR::Value::F32(0.0f))),
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select_f32(y_neg, IR::F32(IR::Value::F32(3.0f)), IR::F32(IR::Value::F32(2.0f))),
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select_f32(z_neg, IR::F32(IR::Value::F32(5.0f)), IR::F32(IR::Value::F32(4.0f))));
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break;
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case IR::Opcode::CubeScF32:
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result = select_face(select_f32(x_neg, z, nz), x, select_f32(z_neg, nx, x));
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break;
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case IR::Opcode::CubeTcF32: result = select_face(ny, select_f32(y_neg, nz, z), ny); break;
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case IR::Opcode::CubeMaF32: {
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const auto two = IR::F32(IR::Value::F32(2.0f));
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result = select_face(IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {x, two})),
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IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {y, two})),
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IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {z, two})));
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break;
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}
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default: return false;
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}
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WriteOperand(inst.dst, result);
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return true;
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}
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} // namespace Libs::Graphics::ShaderRecompiler::Frontend::Detail
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