shader: align float semantics with RDNA2 default mode

src/graphics/shader/recompiler/backend/spirv/spirvEmitterAluHelpers.cpp

@@ -223,12 +223,8 @@ F32Class EmitClassifyF32(EmitterState& state, uint32_t value) {
 	const auto mantissa_bits = EmitAndConstant(state, abs_bits, 0x007fffffu);
 	const auto exponent_max  = EmitCompareU32Constant(state, OpIEqual, exponent_bits, 0x7f800000u);
 	const auto mantissa_nonzero = EmitCompareU32Constant(state, OpINotEqual, mantissa_bits, 0);
-	const auto quiet_bit_clear =
-	    EmitCompareU32Constant(state, OpIEqual, EmitAndConstant(state, cls.bits, 0x00400000u), 0);
-	cls.nan        = EmitLogicalAndBool(state, exponent_max, mantissa_nonzero);
-	cls.snan       = EmitLogicalAndBool(state, cls.nan, quiet_bit_clear);
-	cls.zero       = EmitCompareU32Constant(state, OpIEqual, abs_bits, 0);
-	cls.quiet_bits = EmitOrU32(state, cls.bits, ConstantU32(state, 0x00400000u));
+	cls.nan  = EmitLogicalAndBool(state, exponent_max, mantissa_nonzero);
+	cls.zero = EmitCompareU32Constant(state, OpIEqual, abs_bits, 0);
 	return cls;
 }
 
@@ -308,12 +304,7 @@ uint32_t EmitMinMaxF32Value(EmitterState& state, uint32_t lhs, uint32_t rhs, boo
 
 	const auto rhs_nan_bits =
 	    EmitSelectValueU32(state, rhs_class.nan, lhs_class.bits, numeric_bits);
-	const auto non_snan_bits =
-	    EmitSelectValueU32(state, lhs_class.nan, rhs_class.bits, rhs_nan_bits);
-	const auto rhs_snan_bits =
-	    EmitSelectValueU32(state, rhs_class.snan, rhs_class.quiet_bits, non_snan_bits);
-	const auto result_bits =
-	    EmitSelectValueU32(state, lhs_class.snan, lhs_class.quiet_bits, rhs_snan_bits);
+	const auto result_bits = EmitSelectValueU32(state, lhs_class.nan, rhs_class.bits, rhs_nan_bits);
 	return EmitBitcastU32ToF32(state, result_bits);
 }
 

src/graphics/shader/recompiler/backend/spirv/spirvEmitterInternal.h

@@ -569,11 +569,9 @@ constexpr uint32_t ImageSpirvMultisampled(ImageViewKind view) {
 }
 
 struct F32Class {
-	uint32_t bits       = 0;
-	uint32_t nan        = 0;
-	uint32_t snan       = 0;
-	uint32_t zero       = 0;
-	uint32_t quiet_bits = 0;
+	uint32_t bits = 0;
+	uint32_t nan  = 0;
+	uint32_t zero = 0;
 };
 
 uint32_t PixelParameterMappedLocation(const EmitterState& state, uint32_t attr);

src/graphics/shader/recompiler/frontend/translate/Float.cpp

@@ -89,6 +89,16 @@ bool Translator::TranslateFloat16Operation(const IR::Instruction& inst) {
 		case 3: result = IR::F32(ir.Emit(opcode, {args[0], args[1], args[2]})); break;
 		default: EXIT("invalid half-float source count: %u", inst.src_count);
 	}
+	if (inst.op == IR::Opcode::SqrtF16 || inst.op == IR::Opcode::InverseSqrtF16 ||
+	    inst.op == IR::Opcode::Log2F16) {
+		const auto negative = IR::U1(
+		    ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {args[0], IR::Value::F32(0.0f)}));
+		result = ApplyF32ResultModifiers(inst.dst, result);
+		const auto bits = PackHalf2x16(result, IR::F32(IR::Value::F32(0.0f)));
+		const auto invalid = IR::U32(IR::Value(inst.dst.clamp ? 0u : 0xfe00u));
+		WriteU16(inst.dst, ir.Select(negative, invalid, bits));
+		return true;
+	}
 	WriteF16(inst.dst, result);
 	return true;
 }

tests/ShaderRecompilerComputeTests.cpp

@@ -13705,7 +13705,8 @@ TestCase VectorSpecialF16Ops() {
   code.push_back(EncodeVop1(0x57, 13, Vgpr(2)));
   code.push_back(EncodeVop1(0x57, 14, Vgpr(3)));
   code.push_back(EncodeVop1(0x58, 15, Vgpr(4)));
-  for (u32 i = 0; i < 6; i++) {
+  AppendVop3(&code, 0x1d7, 16, Vgpr(3), 0, 0, 0, 0, true);
+  for (u32 i = 0; i < 7; i++) {
     AppendStoreVgpr(&code, 10 + i, i);
   }
   AppendEnd(&code);
@@ -13714,7 +13715,7 @@ TestCase VectorSpecialF16Ops() {
           code,
           {},
           {0x00008000u, 0xb8005678u, 0x00003800u, 0x00000000u, 0x0000fe00u,
-           0x00000000u},
+           0x00000000u, 0x00000000u},
           {O::V_MOV_B32, O::V_RCP_F16, O::V_RSQ_F16, O::V_LOG_F16, O::V_EXP_F16,
            O::BUFFER_STORE_DWORD, O::S_ENDPGM}};
 }
@@ -14314,8 +14315,8 @@ TestCase VectorMinMaxF32NanAndSignedZeroEdges() {
   return {"VectorMinMaxF32NanAndSignedZeroEdges",
           code,
           {},
-          {0x40000000u, 0x40000000u, 0x80000000u, 0x00000000u, 0x7fe00001u,
-           0x7fe00001u, 0x40000000u, 0x40000000u},
+          {0x40000000u, 0x40000000u, 0x80000000u, 0x00000000u, 0x40000000u,
+           0x40000000u, 0x40000000u, 0x40000000u},
           {O::V_MOV_B32, O::V_MIN_F32, O::V_MAX_F32, O::V_MIN3_F32,
            O::V_MAX3_F32, O::BUFFER_STORE_DWORD, O::S_ENDPGM}};
 }
@@ -14341,7 +14342,7 @@ TestCase VectorMed3F32NanUsesMin3Path() {
   return {"VectorMed3F32NanUsesMin3Path",
           code,
           {},
-          {0x7fe00001u, 0x40000000u, 0x40400000u},
+          {0x40000000u, 0x40000000u, 0x40000000u},
           {O::V_MOV_B32, O::V_MED3_F32, O::BUFFER_STORE_DWORD, O::S_ENDPGM}};
 }