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shader: align float semantics with RDNA2 default mode

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This commit is contained in:
nmzik
2026-08-22 03:16:45 +02:00
parent a2baaccc6e
commit 9241fdc32a
4 changed files with 22 additions and 22 deletions
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src/graphics/shader/recompiler/backend/spirv/spirvEmitterAluHelpers.cpp
+3 -12
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@@ -223,12 +223,8 @@ F32Class EmitClassifyF32(EmitterState& state, uint32_t value) {
const auto mantissa_bits = EmitAndConstant(state, abs_bits, 0x007fffffu);
const auto exponent_max = EmitCompareU32Constant(state, OpIEqual, exponent_bits, 0x7f800000u);
const auto mantissa_nonzero = EmitCompareU32Constant(state, OpINotEqual, mantissa_bits, 0);
const auto quiet_bit_clear =
EmitCompareU32Constant(state, OpIEqual, EmitAndConstant(state, cls.bits, 0x00400000u), 0);
cls.nan = EmitLogicalAndBool(state, exponent_max, mantissa_nonzero);
cls.snan = EmitLogicalAndBool(state, cls.nan, quiet_bit_clear);
cls.zero = EmitCompareU32Constant(state, OpIEqual, abs_bits, 0);
cls.quiet_bits = EmitOrU32(state, cls.bits, ConstantU32(state, 0x00400000u));
cls.nan = EmitLogicalAndBool(state, exponent_max, mantissa_nonzero);
cls.zero = EmitCompareU32Constant(state, OpIEqual, abs_bits, 0);
return cls;
}
@@ -308,12 +304,7 @@ uint32_t EmitMinMaxF32Value(EmitterState& state, uint32_t lhs, uint32_t rhs, boo
const auto rhs_nan_bits =
EmitSelectValueU32(state, rhs_class.nan, lhs_class.bits, numeric_bits);
const auto non_snan_bits =
EmitSelectValueU32(state, lhs_class.nan, rhs_class.bits, rhs_nan_bits);
const auto rhs_snan_bits =
EmitSelectValueU32(state, rhs_class.snan, rhs_class.quiet_bits, non_snan_bits);
const auto result_bits =
EmitSelectValueU32(state, lhs_class.snan, lhs_class.quiet_bits, rhs_snan_bits);
const auto result_bits = EmitSelectValueU32(state, lhs_class.nan, rhs_class.bits, rhs_nan_bits);
return EmitBitcastU32ToF32(state, result_bits);
}
src/graphics/shader/recompiler/backend/spirv/spirvEmitterInternal.h
+3 -5
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@@ -569,11 +569,9 @@ constexpr uint32_t ImageSpirvMultisampled(ImageViewKind view) {
}
struct F32Class {
uint32_t bits = 0;
uint32_t nan = 0;
uint32_t snan = 0;
uint32_t zero = 0;
uint32_t quiet_bits = 0;
uint32_t bits = 0;
uint32_t nan = 0;
uint32_t zero = 0;
};
uint32_t PixelParameterMappedLocation(const EmitterState& state, uint32_t attr);
src/graphics/shader/recompiler/frontend/translate/Float.cpp
+10
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@@ -89,6 +89,16 @@ bool Translator::TranslateFloat16Operation(const IR::Instruction& inst) {
case 3: result = IR::F32(ir.Emit(opcode, {args[0], args[1], args[2]})); break;
default: EXIT("invalid half-float source count: %u", inst.src_count);
}
if (inst.op == IR::Opcode::SqrtF16 || inst.op == IR::Opcode::InverseSqrtF16 ||
inst.op == IR::Opcode::Log2F16) {
const auto negative = IR::U1(
ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {args[0], IR::Value::F32(0.0f)}));
result = ApplyF32ResultModifiers(inst.dst, result);
const auto bits = PackHalf2x16(result, IR::F32(IR::Value::F32(0.0f)));
const auto invalid = IR::U32(IR::Value(inst.dst.clamp ? 0u : 0xfe00u));
WriteU16(inst.dst, ir.Select(negative, invalid, bits));
return true;
}
WriteF16(inst.dst, result);
return true;
}