a833e1b735
graphics: fix vertex and instance IDs for unpatched indirect draws
2026-10-28 04:33:03 +01:00
a5b3673a39
graphics: draw patched-offset indirect draws from GPU-read records
2026-10-27 10:13:15 +01:00
943bc19f46
shader: leave the start instance out of mesh and NGG instance ID VGPRs
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Co-authored-by: Senaxx <michelbeld@gmail.com >
2026-10-26 07:43:11 +01:00
5429888d4c
shader: keep pixel helper lanes out of the EXEC and VCC words
2026-10-26 07:43:11 +01:00
025d1f7edf
shader: decode the SHARED_LIMIT and PRIVATE_LIMIT inline constants
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Co-authored-by: Senaxx <michelbeld@gmail.com >
2026-10-26 06:35:17 +01:00
9dcff95e80
shader: fix crash from packed ancillary used as DPP old operand ( #1769 )
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shader: emit plain EXEC selects for DPP writes that reach every active lane (Street Fighter 6)
2026-10-23 09:51:32 +02:00
da19501889
shader: translate zero-kind branches as the negated nonzero vote
2026-10-21 23:33:30 +02:00
aacf15fd0b
shader: write preserved SDWA fields with one bit-field insert and drop duplicate 16-bit masks
2026-10-21 22:52:14 +02:00
f186b35706
shader: drop null checks on the stage input info pointers
2026-10-20 03:22:40 +02:00
b82512be06
shader: read float inline constants on 64-bit operands as f64 bits ( #1576 )
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A float inline constant (240-248) read by a 64-bit operand is the f64 bit
pattern for integer B64 opcodes too: AMD's compilers emit
v_lshrrev_b64 v[4:5], v0, 1.0 for 0x3ff0000000000000 >> lane. ReadU32Pair
returned {f32 bits, 0}, so only F64-typed reads had the right value.
Based on TheCruZ's 284deab28 (closed #1219 ).
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
2026-10-17 05:21:06 +02:00
b6bd9ecae4
shader: read float inline constants on 16-bit operands as half bits ( #1582 )
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The 16-bit encodings of the float inline constants are fixed: the exact
halves of 0.5, 1.0, 2.0 and 4.0 and their negations, and 0x3118 for
1/(2*pi). Read16LaneBits converted the 32-bit value at run time instead,
through PackHalf2x16, which the AMD driver rounds toward zero, so
1/(2*pi) became 0x3117. Use the encodings directly.
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
2026-10-17 05:05:40 +02:00
c8caa27936
shader: preserve folded native constants for descriptor provenance
2026-10-15 23:22:30 +02:00
9e41d8320a
shader: support returning 64-bit LDS max and compare-exchange
2026-10-13 21:33:50 +00:00
cf77fb4353
shader: initialize NGG vertex count from active native invocations
2026-10-11 01:05:56 +02:00
d247d3d60c
shader: complete signed 64-bit integer comparisons
2026-10-10 03:36:25 +02:00
59183dbfa8
shader: add missing F64 VOPC compares
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Co-authored-by: Hector Mödinger S. <hectormodinger@gmail.com >
2026-10-09 21:01:51 +02:00
bb5edbd490
shader: expose graphics compute queue fields to GETREG
2026-10-09 15:06:39 +00:00
3df456675d
shader: own control flow on IR blocks with direct targets
2026-10-09 01:59:41 +02:00
5297abb7ac
shader: run non-amplifying NGG programs in mesh workgroups
2026-10-07 21:17:35 +04:00
3ba6ebae81
shader: initialize perspective sample barycentrics at SampleId
2026-10-07 20:44:46 +04:00
bb98f26433
shader: add missing I64/U64 compare variants
2026-10-07 05:03:09 +04:00
7a0e1dafd7
shader: classify native half values with shared operand decoding
2026-10-05 18:39:31 +04:00
8274e517b2
shader: add FP64 min, max and rounding
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Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
b8946fef94
shader: translate RDNA2 signed 64-bit not-equal comparisons
2026-10-04 18:39:34 +04:00
284d58d1d5
shader: implement RDNA2 double-precision fractional part
2026-10-04 18:39:34 +04:00
e4aca7a60b
shader: initialize EXEC from requested dispatch thread extents
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Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
2026-10-04 18:39:34 +04:00
0d0b215fab
shader: port 64-bit ALU and atomic opcodes
2026-10-02 00:51:15 +04:00
11001c97f7
shader: add distinct mesh shader type
2026-10-02 00:51:15 +04:00
337f432016
shader: execute PS5 BVH intersections and local FLAT stacks
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Jean-Philippe <github@meunier.jp >
2026-10-02 00:51:15 +04:00
581dad7dd3
shader: implement RDNA2 FP64 equality comparisons
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Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-02 00:51:15 +04:00
bc193f5272
shader: V_CMPX_LT_I16 + fix SDWA with SEXT
2026-09-30 20:49:20 +04:00
0a5774be7b
shader: support FP64 conversions used by FighterZ ( #884 )
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shader: support float and unsigned widening to FP64
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-28 17:39:31 +04:00
0791f921f6
UFC 5 in-game ( #883 )
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* shader: release descriptor dependencies
* shader: simplify shared-exit control flow
* shader: fix scalar memory loads
* shader: fix LDS counter bounds
* renderer: skip inactive pixel shaders
* shader: respect FP32 mode in comparisons
* renderer: fix sampler border colors
* shader: resolve descriptors from control flow
* shader: resolve descriptors before resource planning
* shader: handle scalar guards for image bounds
* shader: handle reduced guards for image loops
* shader: fix wave guards and material indices
* shader: preserve scalar buffer offset alignment and carry
* shader: prove masked loop bounds across iteration transitions
* shader: preserve source and IR before resource tracking failures
* shader: track material keys selected from active lanes
* shader: remove obsolete post-dominator analysis
* shader: follow bounds guards through control-flow joins
2026-09-28 16:03:05 +04:00
16b83a034c
Shader: execute RDNA2 FP64 shadow arithmetic and log denorm limits
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Shader: disable FP64 denorm preservation controls for now
2026-09-26 15:15:35 +04:00
7d7267cc56
Translate NGG mesh prolog with guest wave32 width
2026-09-23 22:50:51 +04:00
476204cd4b
Initialize native NGG vertex launch state and wave size
2026-09-22 11:11:36 +04:00
95d3d9d3ad
shader: fix packed integer negation
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-09-18 09:11:55 +04:00
bfc8cd0e0b
shader: DPP8 moves
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Co-authored-by: foufouadi <attar.foued@gmail.com >
Co-authored-by: fxpw <fxpw@outlook.com >
2026-09-18 09:11:55 +04:00
7c9148dd47
Support triangle fans in PS5 geometry shaders
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Keep the fan center across subgroups and reuse the existing index fetch.
2026-09-16 08:42:47 +04:00
0d9e95d96a
Fix centroid interpolation weights
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PPSA03792
2026-09-15 19:51:30 +04:00
a1fbc41146
Preserve shared scalar loads during embedded vertex fetch replacement
2026-09-15 11:24:05 +04:00
7516068662
gpu: compile RDNA2 tessellation through native LS HS and TES stages
2026-09-14 06:58:32 +04:00
5a31de7955
shader: keep derived frontend metadata with its owner
2026-09-12 13:42:15 +04:00
1d1f00bdef
shader: use Khronos definitions and simplify compiler ownership
2026-09-12 13:42:15 +04:00
c913951f7b
shader: implement RDNA2 subvector loop mask and branch semantics
2026-09-10 14:11:46 +04:00
1af19eabf0
shader: fix incorrect per-lane VCCZ/EXECZ reads
2026-09-09 13:22:09 +04:00
ef0155636a
shader: support single and split NGG shaders for PPSA11142
2026-09-08 21:26:59 +04:00
839c172612
shader: reuse operands and remove duplicate helpers
2026-09-08 21:26:59 +04:00
72963b01e1
shader: remove redundant decoder and translator state
2026-09-08 21:26:59 +04:00
6cc9e5de11
shader: fix wave32 VCC halves and scalar mask moves
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Co-authored-by: Brandon Strong <brandostrong@gmail.com >
2026-09-07 06:04:40 +04:00
nmzik