f3dc5ee4a9
Collect shader interface metadata in place without copying resources
2026-10-02 16:07:16 +04:00
95c89229ad
Remove dead shader instruction cycles with linear liveness traversal
2026-10-02 15:49:43 +04:00
7804eef9b6
Lower finite GPU-selected image descriptors through shared indirect bindings
2026-10-02 15:37:17 +04:00
d1c99bbfb0
Consolidate instruction operand bounds checks
2026-10-02 13:24:03 +04:00
28f29b8e6f
Inline common IR operands and share storage with Phi pairs
2026-10-02 13:24:03 +04:00
3353c1ff3b
shader: pack the runtime evaluation index beside the IR opcode
2026-10-02 13:24:03 +04:00
b3e419ff11
shader: implement 32-bit RDNA2 IMAGE_ATOMIC_CMPSWAP ( #952 )
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* shader: implement 32-bit RDNA2 image atomic compare-and-swap
* shader: share atomic emission and correct image barriers
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-02 01:15:53 +04:00
2b2915e271
Reuse SSA read traversal storage within each pass
2026-10-02 00:53:51 +04:00
7101741637
Cache SPIR-V arithmetic types lazily in existing emitters
2026-10-02 00:53:51 +04:00
f29bd0fe35
Reuse whole-wave ballot and first-lane SPIR-V results
2026-10-02 00:51:15 +04:00
35759e48cf
shader: expose wave32 feature guards through ballot mask simplification
2026-10-02 00:51:15 +04:00
6409be2874
shader: respect branch reachability when refreshing scalar resources
2026-10-02 00:51:15 +04:00
0d0b215fab
shader: port 64-bit ALU and atomic opcodes
2026-10-02 00:51:15 +04:00
11001c97f7
shader: add distinct mesh shader type
2026-10-02 00:51:15 +04:00
337f432016
shader: execute PS5 BVH intersections and local FLAT stacks
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Jean-Philippe <github@meunier.jp >
2026-10-02 00:51:15 +04:00
581dad7dd3
shader: implement RDNA2 FP64 equality comparisons
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Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-02 00:51:15 +04:00
64dcbe0ea1
shader: decode the combined conditional-debug branch
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Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com >
2026-10-02 00:51:15 +04:00
bc193f5272
shader: V_CMPX_LT_I16 + fix SDWA with SEXT
2026-09-30 20:49:20 +04:00
73615c31ff
graphics: preserve logical alpha when blending reordered targets (PPSA02721)
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Co-authored-by: EmK530 <admin@emk530.net >
2026-09-29 19:52:40 +04:00
6799ecbc5b
shader: add native 64-bit LDS OR with shared typed storage views
2026-09-29 19:13:33 +04:00
35c4dca2ce
shader: add V_CMPX_NLE_F16 opcode
2026-09-29 19:13:33 +04:00
c8baa7b909
shader: derive immutable resource policy once per plan
2026-09-28 18:01:49 +04:00
2016f8e2fe
gpu: address extended guest memory without widening dense cache tables
2026-09-28 18:01:49 +04:00
0a5774be7b
shader: support FP64 conversions used by FighterZ ( #884 )
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shader: support float and unsigned widening to FP64
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-28 17:39:31 +04:00
0791f921f6
UFC 5 in-game ( #883 )
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* shader: release descriptor dependencies
* shader: simplify shared-exit control flow
* shader: fix scalar memory loads
* shader: fix LDS counter bounds
* renderer: skip inactive pixel shaders
* shader: respect FP32 mode in comparisons
* renderer: fix sampler border colors
* shader: resolve descriptors from control flow
* shader: resolve descriptors before resource planning
* shader: handle scalar guards for image bounds
* shader: handle reduced guards for image loops
* shader: fix wave guards and material indices
* shader: preserve scalar buffer offset alignment and carry
* shader: prove masked loop bounds across iteration transitions
* shader: preserve source and IR before resource tracking failures
* shader: track material keys selected from active lanes
* shader: remove obsolete post-dominator analysis
* shader: follow bounds guards through control-flow joins
2026-09-28 16:03:05 +04:00
496432bbb4
Shader: skip identity image remapping on materialization hits
2026-09-27 10:47:18 +04:00
bec67b7863
Fix HITMAN 3 boot, layered presentation, and socket imports ( #851 )
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* videoout: synchronize layered flips with premultiplied composition
* shader: support unsigned FFBH subword sources
* shader: apply cube-face result scaling
* shader: prune buffer reads proven out of bounds
* net: implement send and receive exports with shared socket handling
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-27 02:13:30 +04:00
81f312638f
graphics: encode packed UNorm buffer stores before writing skinning normals
2026-09-26 23:42:19 +04:00
16b83a034c
Shader: execute RDNA2 FP64 shadow arithmetic and log denorm limits
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Shader: disable FP64 denorm preservation controls for now
2026-09-26 15:15:35 +04:00
cf268af839
Shader: implement RDNA2 image atomic float maximum
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Shader: implement RDNA2 image atomic float minimum
Co-authored-by: foufouadi <attar.foued@gmail.com >
Co-authored-by: frans <francois.att@gmail.com >
Co-authored-by: fxpw <fxpw@outlook.com >
Co-authored-by: Matthew Hurley <171001439+theantipopau@users.noreply.github.com >
2026-09-26 15:15:35 +04:00
cda236dbb3
Shader recompiler: accept V_NOT_B32 SDWA partial dst with any source; allow 64 buffers
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SDWA source extraction and destination insertion are independent. Cover the reported word1-to-word0 preserve form and byte-source partial destinations in compute tests. Verify 64 distinct compute buffers survive resource tracking and binding layout, and remove the obsolete CFG rejection.
(cherry picked from commit 9e74df7dc0
2026-09-26 01:58:55 +04:00
3585cd8f03
shader: simplify translator dispatch to void handlers
2026-09-25 14:27:09 +04:00
ff54608569
shader: add V_CMPX_O_F32 opcode
2026-09-25 14:27:09 +04:00
6bb68a3fd9
shader: stop repeated CFG merge gateway splitting
2026-09-25 14:27:09 +04:00
93185953f1
shader: fuse image specialization setup with materialization
2026-09-25 14:27:09 +04:00
5a705dd15f
shader: support V_CMPX_EQ_U16 ( #816 )
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* shader: support V_CMPX_EQ_U16
Decode gfx11 VOPC 0xba and lower it as an unsigned 16-bit equality
compare with CMPX EXEC-mask semantics.
🤖 Generated with Codebuff 🤖
Co-Authored-By: Codebuff <noreply@codebuff.com >
* shader: correct CMPX EQ U16 runtime expectations
Remove the added CFG tests and correct two EXEC expectations in the compute regression case.
---------
Co-authored-by: Matthew Hurley <171001439+theantipopau@users.noreply.github.com >
Co-authored-by: Codebuff <noreply@codebuff.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-25 02:27:44 +04:00
d72a79af2d
graphics: skip compute dispatches with BVH instructions
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Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
dc9280d75d
shader: add GLC/DLC buffer cache policy support
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Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
6a9ae4ae43
shader: add SDWA support for V_MAX_I32
2026-09-24 20:46:04 +04:00
392f39e2f6
shader: support indirect BUFFER_LOAD_DWORDX3
2026-09-24 20:46:04 +04:00
e43c242683
shader: add S_MEMREALTIME opcode
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Co-authored-by: Maxime Allanic <maxime@allanic.me >
Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
fcf0f3b67e
shader: fold the lane test after a pixel shader's entry s_wqm ( #801 )
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Preserve live lane predicates through RDNA2 whole-quad expansion
Keep the source-live predicate when WQM expands a scalar mask, so entry masks remain known live without an instruction pre-scan. Preserve scalar mask values, SCC, half writes, and raw-source behavior.
Cover entry pixel masks, cross-half copies, and scalar/high-word sources with existing shader regression suites.
Co-authored-by: nmzik <Nmzik@mail.ru >
Co-authored-by: Douglas <douglasproducoes21@gmail.com >
2026-09-24 12:02:19 +04:00
a6248c7c7c
Convert formatted half-float buffer stores from F32
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Co-authored-by: TarkusR <90155059+TarkusR@users.noreply.github.com >
2026-09-24 11:13:33 +04:00
963a0817dc
Bound uniformized image keys by guarded material mask
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Co-authored-by: TarkusR <90155059+TarkusR@users.noreply.github.com >
2026-09-24 11:13:33 +04:00
1617ee77e5
Share CFG reachability for descriptor bounds analysis
2026-09-24 11:13:33 +04:00
3b89e36d1e
Track bounded indirect image tables from signed shader loops
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Co-authored-by: TarkusR <90155059+TarkusR@users.noreply.github.com >
2026-09-24 11:13:33 +04:00
3dc3fd0197
shader: implement DS_INC_U32 and DS_DEC_U32 ( #790 )
2026-09-24 00:45:12 +04:00
fc86509aac
shader: support DS_WRITE_B8_D16_HI ( #794 )
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Decode GFX10 DS opcode 0xa0 as DS_WRITE_B8_D16_HI (next to
DS_WRITE_B16_D16_HI at 0xa1) and lower it through the existing 8-bit
shared-memory write. The stored byte is bits 23:16 of the data VGPR,
selected with SDWA BYTE_2 on src1.
Add captured-instruction decode coverage (from GTA V, PPSA04264) and a
runtime regression that writes one byte of a distinctive source value
into a pre-filled LDS dword.
2026-09-24 00:44:39 +04:00
7d7267cc56
Translate NGG mesh prolog with guest wave32 width
2026-09-23 22:50:51 +04:00
5ed5fdd36e
Preserve resource level bits in texture descriptors
2026-09-23 15:41:02 +04:00
nmzik