ff61c1cecd
shader: implement V_SIN_F16 ( #399 )
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Co-authored-by: nmzik <Nmzik@mail.ru >
2026-08-30 01:32:49 +04:00
1a87cfedb5
shader: implement V_COS_F16
2026-08-29 19:23:19 +04:00
5bd447d2a2
shader: implement DS_BPERMUTE_B32
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Co-authored-by: Techx3 <56268269+Techx3@users.noreply.github.com >
2026-08-29 19:23:19 +04:00
fcc9dff5b9
shader: DS_WRITE_B16_D16_HI
2026-08-29 14:40:13 +04:00
d9ae3ed64c
shader: V_FFBH_I32
2026-08-29 14:03:57 +04:00
dca7ece2ca
shader: legalize 1D level-zero gathers
2026-08-29 13:32:20 +04:00
53a59434d8
shader: implement V_CMP_EQ_U64
2026-08-29 11:26:05 +04:00
18b6c9059b
shader: support DS_READ_U16_D16_HI ( #356 )
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Decode the high-half D16 LDS read and route it through the existing unsigned-short load lowering. Represent the destination as a high-half partial write so the low 16 bits of the VGPR remain intact. Add captured-instruction decode coverage and a Vulkan execution regression that verifies the preserved half.
Co-authored-by: SueryRD <the.ai.tester2@gmail.com >
2026-08-29 10:39:45 +04:00
b02eb28fd1
shader: support SDWA byte left-shift counts
2026-08-29 10:03:13 +04:00
07f1e77d23
shader: support SDWA byte shift counts
2026-08-29 10:03:13 +04:00
c167375fe1
shader: centralize program compilation and permutation caching
2026-08-27 13:37:46 +02:00
e738535294
graphics: add RDNA2 FLAT BDA buffer cache and faults
2026-08-27 03:45:41 +02:00
ab50c10d08
graphics: split shader translation into explicit opcode dispatchers
2026-08-26 08:49:39 +02:00
ffa69d48de
shader: remove second IR layer
2026-08-26 08:49:39 +02:00
bc9c70d50f
shader: implement RDNA2 V_LSHLREV_B64
2026-08-23 16:39:01 +02:00
8d01fb1c18
shader: DS_READ_U16_D16, V_LSHRREV_B64,
2026-08-23 01:19:47 +02:00
a610528075
shader: V_CMPX_NE_I64
2026-08-23 00:59:44 +02:00
3e25eb0998
Fix wave64 LDS synchronization on subgroup32 hosts
2026-08-23 00:46:37 +02:00
0d92ce49da
shader: support RDNA2 V_CMPX_NE_U64
2026-08-22 04:38:13 +02:00
4179bb5b06
shader: route inner shared exits first
2026-08-22 04:00:37 +02:00
d581703ab4
shader: preserve folded control-flow values
2026-08-22 03:31:59 +02:00
a2baaccc6e
shader: fix auxiliary position exports
2026-08-22 02:58:35 +02:00
5e64efce4f
graphics: support RDNA2 custom pixel interpolation
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Co-authored-by: Senaxx <Senaxx@users.noreply.github.com >
2026-08-21 23:33:40 +02:00
bad6726f5e
Rewrite descriptor bindings and unify graphics push constants
2026-08-21 22:28:10 +02:00
49ea1680f8
graphics: use per-invocation shader masks
2026-08-21 08:03:22 +02:00
79443aa104
shader: decode compressed UNORM16 MRT exports
2026-08-21 05:23:09 +02:00
d0a4c908a1
shader: align address-memory buffer bindings
2026-08-21 03:32:49 +02:00
770bdb9571
shader: separate formatless storage from image atomics
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
Co-authored-by: Senaxx <Senaxx@users.noreply.github.com >
2026-08-21 03:32:49 +02:00
ebd47081ca
agc: initialize interpolant mapping registers
2026-08-21 03:32:49 +02:00
88c351f0fa
shader: canonicalize SampleAdjust sampler scratch bits
2026-08-21 03:32:48 +02:00
7f66a61801
shader: reject rejoining early-exit routes
2026-08-21 03:32:48 +02:00
2bd9f4124f
shader: structurize nested early-exit tails
2026-08-21 03:32:48 +02:00
705fc93363
shader: initialize compute EXEC from active subgroup
2026-08-21 03:32:48 +02:00
77db9164b8
graphics: continue compute on native subgroup size
2026-08-21 03:32:48 +02:00
a42e3bb09e
graphics: derive compute wave size from dispatch mode
2026-08-21 03:32:48 +02:00
56a15c2036
Implement RDNA2 per-invocation scratch memory
2026-08-21 03:32:47 +02:00
2db0b3cfa7
shader: fix shared-terminal selection merges
2026-08-21 03:32:47 +02:00
4710522e87
shader: canonicalize CFG loop headers
2026-08-21 03:32:47 +02:00
85cf965d54
refactor(shader): centralize typed resource metadata
2026-08-21 03:32:47 +02:00
87166eed94
refactor(shader): reduce dispatcher state overhead
2026-08-21 03:32:47 +02:00
6e9f162bd4
refactor(shader): compact paired 64-bit lowering
2026-08-21 03:32:47 +02:00
8063822243
refactor(shader): preserve native scalar memory operations
2026-08-21 03:32:47 +02:00
c236ba713d
refactor(shader): preserve native wide shared operations
2026-08-21 03:32:47 +02:00
c9e942a972
refactor(shader): compact whole-quad mask lowering
2026-08-21 03:32:47 +02:00
5383972e96
refactor(shader): preserve native wide buffer operations
2026-08-21 03:32:47 +02:00
3ea2099245
refactor(shader): simplify buffer access emission
2026-08-21 03:32:47 +02:00
49145c1902
refactor(shader): emit structured phis natively
2026-08-21 03:32:47 +02:00
d34e30d892
refactor(shader): emit SPIR-V declarations on demand
2026-08-21 03:32:47 +02:00
e1bcc298a0
refactor(shader): remove register-state compatibility paths
2026-08-21 03:32:47 +02:00
33545ca6c4
test(shader): establish SPIR-V size baselines
2026-08-21 03:32:47 +02:00
Mehmet Cambaz