a5b3673a39
graphics: draw patched-offset indirect draws from GPU-read records
2026-10-27 10:13:15 +01:00
db12f0c5fb
shader: select consecutive GPU-selected sampler table entries without a switch
2026-10-27 04:23:01 +01:00
95a507a8ff
shader: support 64-bit buffer atomic minimum
2026-10-27 04:23:01 +01:00
78adb9293d
shader: give A16 1D and late 3D gradients their own address VGPRs
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-27 04:23:01 +01:00
5429888d4c
shader: keep pixel helper lanes out of the EXEC and VCC words
2026-10-26 07:43:11 +01:00
ceb154d9e4
shader: acquire stored buffers and images at S_BARRIER
2026-10-26 05:32:02 +01:00
26ca609236
shader: type pixel outputs of UINT and SINT render targets as integer vectors
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
2026-10-26 05:32:02 +01:00
4ebae87a1b
shader: apply the LOD clamp of image_sample _cl variants
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Co-authored-by: Senaxx <michelbeld@gmail.com >
2026-10-26 05:32:02 +01:00
6357740fa1
shader: lower wave32 whole-wave UMin and UMax reductions to subgroup reductions
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Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
2026-10-26 05:32:02 +01:00
ba7f9969ef
shader: bound storage buffers by pushed binding sizes instead of OpArrayLength
2026-10-26 05:32:02 +01:00
72903bfce6
shader: use the V_PERMLANE16 row directly instead of copying it
2026-10-25 02:20:44 +02:00
59d8256b36
shader: encode 11/10-bit float formatted buffer stores as truncated unsigned floats
2026-10-25 02:20:44 +02:00
9a20c6f738
shader: disable DPP16 writes from EXEC-disabled sources without BOUND_CTRL
2026-10-25 02:20:44 +02:00
67c89e0915
shader: keep the old V_PERMLANE16 destination for inactive sources without BOUND_CTRL
2026-10-25 02:20:44 +02:00
e864cb20bd
shader: clamp V_FRACT_F16/F32/F64 results below one
2026-10-25 02:20:44 +02:00
77a8f30758
shader: read S_MEMREALTIME from the host device clock shifted to about 100 MHz
2026-10-23 19:48:53 +02:00
706aa030ad
shader: extract 9-bit NGG primitive vertex indices, leaving the edge flags out
2026-10-23 19:48:53 +02:00
9dcff95e80
shader: fix crash from packed ancillary used as DPP old operand ( #1769 )
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shader: emit plain EXEC selects for DPP writes that reach every active lane (Street Fighter 6)
2026-10-23 09:51:32 +02:00
27dc7c281f
graphics: keep bounded image heaps resident in a bindless descriptor set
2026-10-23 07:17:57 +02:00
79837b423d
graphics: support compute stores to 2D MSAA images
2026-10-22 22:11:06 +02:00
aafe014d0c
shader: read raw D16 depth bits through kDepth k16UInt image loads
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Co-authored-by: Artyom Zabroda <artyomzabroda@proton.me >
2026-10-22 22:11:06 +02:00
a951a91703
spirv: emit OpName only with debug info
2026-10-22 22:11:06 +02:00
d7c1896647
shader: interpolate f16 parameter halves (V_INTERP_P1LL_F16, V_INTERP_P2_F16) ( #1792 )
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shader: interpolate packed f16 attributes for v_interp_p1ll_f16 and v_interp_p2_f16
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-22 04:54:10 +02:00
919fac13d0
shader: read lane 0 in V_READFIRSTLANE when EXEC is zero instead of an undefined lane
2026-10-22 01:20:54 +02:00
a52d1ed4e2
shader: drop the 64-bit min/max NaN-lhs select the ordered compare already covers
2026-10-22 01:09:09 +02:00
a3aece2762
shader: check the DPP source lane bound only for row shifts
2026-10-22 01:02:38 +02:00
64186404a3
shader: load the DPP lane id once for both partial write masks
2026-10-22 01:01:38 +02:00
11465a5e3c
shader: drop the large-input select before sin and cos since fract already returns zero
2026-10-22 00:44:43 +02:00
09a9654458
shader: compute DPP permute, rotate, mirror and share lanes with bit-field and XOR ops
2026-10-22 00:40:07 +02:00
6123419437
shader: skip full DPP row and bank masks and test partial ones with one bit extract
2026-10-22 00:35:09 +02:00
8177969f33
shader: branch to the pixel kill on the inverted targets instead of negating the condition
2026-10-22 00:33:07 +02:00
ce54aa8d14
shader: return the first source when both 64-bit min/max inputs are NaN
2026-10-22 00:28:43 +02:00
3bb09ed2a4
shader: clamp before float-to-int conversion and drop the redundant truncate
2026-10-22 00:26:40 +02:00
1e4ac1371d
shader: return the first source when both float min/max inputs are NaN
2026-10-22 00:00:04 +02:00
93071ebdf8
shader: drop the denormal flush before exp2
2026-10-21 23:33:42 +02:00
3a842e1a6b
shader: flush FP32 denormals with a float compare and multiply instead of bit masks
2026-10-21 23:33:42 +02:00
0f7d112545
shader: emit constant-true guarded blocks inline and fold immediate constant-buffer indices
2026-10-21 23:27:04 +02:00
10a852c2ac
shader: pack 16-bit lane pairs with one bit-field insert
2026-10-21 22:46:04 +02:00
4a1440197f
shader: share one find-first-bit lowering for S_FF0/FF1/FLBIT_I32_B64 and remove FindUMsb64
2026-10-21 22:39:34 +02:00
6e5167598e
shader: compute add-with-carry with compares and remove IAddCarry32
2026-10-21 22:28:11 +02:00
c571d8ed5a
shader: remove IR opcodes and IREmitter helpers that nothing produces
2026-10-21 22:19:26 +02:00
286481889f
shader: emit float min/max as host instructions on AMD GPUs ( #1761 )
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* shader: emit float min/max as host instructions on AMD GPUs
V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.
In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.
Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.
Developed with AI assistance (Claude Code).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: gate host float min/max on RADV and check the emitted instructions
* shader: drop float controls 2 from host float min/max
* shader: drop the float min/max env override and atomic flag
* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device
* shader: enable host float min/max on AMD GPUs
---------
Co-authored-by: arda <ardaeska@gmail.com >
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 21:36:08 +02:00
ea1b032c59
shader: drop the unread F32Class bits and the per-pass HS reflection counter reset
2026-10-20 23:54:32 +02:00
3c4124dafa
shader: emit F32 min/max as exact compare-selects, MED3 with one max and saturate as NClamp
2026-10-20 23:36:26 +02:00
8cc5f5364a
shader: share SMEM load results across emulated wave64 halves
2026-10-20 22:32:48 +02:00
1ce663b5a9
shader: lower HS neighbour LDS reads, control-point output read-back, looped HS reflection and integer partitioning
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Co-authored-by: NeySlim <4509984+NeySlim@users.noreply.github.com >
2026-10-20 22:18:00 +02:00
0957f088ad
shader: reflect HS patch constants and lower TES patch inputs through predicated addresses
2026-10-20 15:21:19 +02:00
f0e462a8a2
shader: allocate split-wave dispatcher spill IDs in program order
2026-10-20 15:21:19 +02:00
feed075a9f
gpu: implement PA_CL_UCP user clip planes through draw push constants
2026-10-20 15:21:19 +02:00
f186b35706
shader: drop null checks on the stage input info pointers
2026-10-20 03:22:40 +02:00
nmzik