nmzik
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1d3fd07fe6
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shader: share indirect buffer format geometry lookup
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2026-10-15 22:28:01 +02:00 |
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nmzik
|
50844badbf
|
shader: map debug SPIR-V blocks to native RDNA2 PCs
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2026-10-15 22:28:01 +02:00 |
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nmzik
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c1f6838e40
|
shader: share repeated raw indirect buffer load bodies
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2026-10-15 22:28:01 +02:00 |
|
nmzik
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1039c54f5d
|
shader: share indirect buffer array access after an empty root
Co-authored-by: fxpw <fxpw@outlook.com>
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2026-10-14 21:17:44 +02:00 |
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nmzik
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b24ce3440d
|
shader: track buffer liveness and offsets by resource count
Co-authored-by: fxpw <fxpw@outlook.com>
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2026-10-14 21:11:14 +02:00 |
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nmzik
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127cf8d46f
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shader: route image stores through shared indirect descriptor access
Co-authored-by: fxpw <fxpw@outlook.com>
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2026-10-14 18:39:40 +02:00 |
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nmzik
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150bcb06a9
|
shader: share runtime buffer format conversion across loads
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2026-10-14 14:29:40 +02:00 |
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nmzik
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26d326d1b0
|
shader: share bounded record descriptors for packed loads and byte stores
Co-authored-by: fxpw <fxpw@outlook.com>
|
2026-10-14 05:07:24 +02:00 |
|
nmzik
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c11254a996
|
shader: share format conversion for packed normalized image stores
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2026-10-13 21:27:07 +00:00 |
|
nmzik
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e2c8b61de6
|
shader: remove unreachable mixed image specialization paths
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2026-10-13 21:27:07 +00:00 |
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nmzik
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f01a3750d4
|
shader: validate indirect image operands at each typed access
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2026-10-13 21:27:07 +00:00 |
|
Ali Almohaya
|
460a196fca
|
shader: emit dynamic sample offsets with the enabled maintenance8 feature
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2026-10-13 21:27:07 +00:00 |
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nmzik
|
fd66f580b4
|
shader: resolve packed buffer selectors with shared indexed stores
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com>
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2026-10-13 21:27:07 +00:00 |
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nmzik
|
8c81386568
|
shader: share finite descriptor planning with GPU-selected inline samplers
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2026-10-09 15:06:39 +00:00 |
|
nmzik
|
ee4dd90649
|
shader: emit native integer operations and remove signedness casts
|
2026-10-09 02:54:21 +02:00 |
|
nmzik
|
46997dfc7a
|
shader: retain resource type IDs in SPIR-V emission state
|
2026-10-09 01:55:50 +02:00 |
|
nmzik
|
e1ac893a0c
|
shader: collect usage once and emit descriptor slots directly
|
2026-10-09 02:17:38 +04:00 |
|
nmzik
|
52dbc724f8
|
shader: store SPIR-V definitions directly in IR nodes
|
2026-10-09 01:40:41 +04:00 |
|
nmzik
|
5b826c6e4a
|
shader: emit native 64-bit operations where compatible
|
2026-10-05 20:41:03 +04:00 |
|
nmzik
|
7a0e1dafd7
|
shader: classify native half values with shared operand decoding
|
2026-10-05 18:39:31 +04:00 |
|
nmzik
|
e85279ea7b
|
shader: correct DS float min/max operands and special values
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
|
2026-10-05 04:11:48 +04:00 |
|
nmzik
|
b0bbaef1eb
|
gpu: store large compute shared memory in device buffers
|
2026-10-05 02:24:51 +04:00 |
|
nmzik
|
39248a1f87
|
shader: emit per-vertex mesh clip and cull distances
Co-authored-by: Senaxx <michelbeld@gmail.com>
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
|
2026-10-04 18:39:34 +04:00 |
|
nmzik
|
c3f4962715
|
shader: use native narrow storage for byte-aligned PS5 buffers
Co-authored-by: MehmetCambaz <mcambaz18@gmail.com>
|
2026-10-04 18:39:34 +04:00 |
|
nmzik
|
843b577880
|
shader: resolve bounded GPU material keys through sampled image arrays
Co-authored-by: TheCruZ <thecruzwtf@gmail.com>
|
2026-10-04 18:39:34 +04:00 |
|
nmzik
|
a55a28380d
|
shader: decode GPU-selected formatted buffer loads with native bounds
Co-authored-by: TheCruZ <thecruzwtf@gmail.com>
|
2026-10-04 18:39:34 +04:00 |
|
nmzik
|
f58014ff0e
|
shader: preserve wave-wide vector-store completion before publication
|
2026-10-04 18:39:34 +04:00 |
|
nmzik
|
429d0af62b
|
shader: bind bounded GPU-selected buffer store destinations
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com>
|
2026-10-04 18:39:34 +04:00 |
|
frans
|
bd611bfe15
|
Honor explicit gather LOD with shared image mip selection
Co-authored-by: YuhiAida <21134775+YuhiAida@users.noreply.github.com>
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com>
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
Co-authored-by: Senaxx <michelbeld@gmail.com>
Co-authored-by: Mac <me@itsmemac.com>
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com>
|
2026-10-03 14:19:33 +04:00 |
|
Louis
|
b3e419ff11
|
shader: implement 32-bit RDNA2 IMAGE_ATOMIC_CMPSWAP (#952)
* shader: implement 32-bit RDNA2 image atomic compare-and-swap
* shader: share atomic emission and correct image barriers
---------
Co-authored-by: nmzik <Nmzik@mail.ru>
|
2026-10-02 01:15:53 +04:00 |
|
nmzik
|
7101741637
|
Cache SPIR-V arithmetic types lazily in existing emitters
|
2026-10-02 00:53:51 +04:00 |
|
nmzik
|
337f432016
|
shader: execute PS5 BVH intersections and local FLAT stacks
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com>
Co-authored-by: Mac <me@itsmemac.com>
Co-authored-by: Senaxx <michelbeld@gmail.com>
Co-authored-by: Jean-Philippe <github@meunier.jp>
|
2026-10-02 00:51:15 +04:00 |
|
nmzik
|
6799ecbc5b
|
shader: add native 64-bit LDS OR with shared typed storage views
|
2026-09-29 19:13:33 +04:00 |
|
nmzik
|
16b83a034c
|
Shader: execute RDNA2 FP64 shadow arithmetic and log denorm limits
Shader: disable FP64 denorm preservation controls for now
|
2026-09-26 15:15:35 +04:00 |
|
nmzik
|
dc9280d75d
|
shader: add GLC/DLC buffer cache policy support
Co-authored-by: Mac <me@itsmemac.com>
|
2026-09-24 20:46:04 +04:00 |
|
nmzik
|
8a5e5c5476
|
Fold buffer address identities and remove empty predicates
|
2026-09-23 15:41:02 +04:00 |
|
nmzik
|
bfc8cd0e0b
|
shader: DPP8 moves
Co-authored-by: foufouadi <attar.foued@gmail.com>
Co-authored-by: fxpw <fxpw@outlook.com>
|
2026-09-18 09:11:55 +04:00 |
|
nmzik
|
5dc644edb4
|
clean up graphics helpers
|
2026-09-17 20:35:36 +04:00 |
|
nmzik
|
86414760e6
|
Cull zero homogeneous vertex positions before rasterization
Fix Playroom top right artifact on Nvidia by clipping zero-position vertices.
|
2026-09-15 11:24:05 +04:00 |
|
nmzik
|
87971a28f5
|
gpu: isolate tessellation analysis and SPIR-V emission
|
2026-09-14 06:58:32 +04:00 |
|
nmzik
|
7516068662
|
gpu: compile RDNA2 tessellation through native LS HS and TES stages
|
2026-09-14 06:58:32 +04:00 |
|
nmzik
|
1208d22547
|
Fix Windows Clang SPIR-V serialization with typed operands
|
2026-09-12 13:08:23 +02:00 |
|
nmzik
|
2d37634ee9
|
shader: construct SPIR-V module variables in one place
|
2026-09-12 13:42:15 +04:00 |
|
nmzik
|
20e57994cf
|
shader: reuse native emitters and simplify memory dispatch
|
2026-09-12 13:42:15 +04:00 |
|
nmzik
|
59ef88c959
|
shader: generate SPIR-V dispatch and marshal handler arguments
|
2026-09-12 13:42:15 +04:00 |
|
nmzik
|
1d1f00bdef
|
shader: use Khronos definitions and simplify compiler ownership
|
2026-09-12 13:42:15 +04:00 |
|
nmzik
|
fcef691e0a
|
shader: drop EmitTrueBool
|
2026-09-08 21:26:59 +04:00 |
|
nmzik
|
9f49ac8249
|
shader: reuse SPIR-V helpers and memory resources
|
2026-09-08 21:26:59 +04:00 |
|
nmzik
|
2b3993a595
|
shader: share emitter helpers
|
2026-09-08 21:26:59 +04:00 |
|
nmzik
|
cd62693792
|
shader: share control flow labels
|
2026-09-08 21:26:59 +04:00 |
|