59d8256b36
shader: encode 11/10-bit float formatted buffer stores as truncated unsigned floats
2026-10-25 02:20:44 +02:00
9a20c6f738
shader: disable DPP16 writes from EXEC-disabled sources without BOUND_CTRL
2026-10-25 02:20:44 +02:00
67c89e0915
shader: keep the old V_PERMLANE16 destination for inactive sources without BOUND_CTRL
2026-10-25 02:20:44 +02:00
e864cb20bd
shader: clamp V_FRACT_F16/F32/F64 results below one
2026-10-25 02:20:44 +02:00
ec8b75b244
pipeline: persist shaders and pipelines per game and prewarm them at boot
2026-10-25 02:20:44 +02:00
9210264d47
shader: saturate V_CVT_PK_U16_U32 and V_CVT_PK_I16_I32
2026-10-25 02:20:44 +02:00
87e49282b8
pipeline: log real shader compiles to the console
2026-10-25 02:20:44 +02:00
1816004357
shader: serialize resource plans for the shader cache
2026-10-25 02:20:44 +02:00
bfc377627a
pipeline: create pipelines from GraphicsPipelineKey and shader modules
2026-10-25 02:20:44 +02:00
4b651f2ba7
pipeline: fold the program cache into PipelineCache with stable module ids
2026-10-25 02:20:44 +02:00
dbc7b8b2ff
pipeline: look up draw programs and pipelines from the command buffer
2026-10-24 05:18:46 +02:00
269e411ef2
graphics: index live cache slots directly
2026-10-24 04:26:16 +02:00
170c107779
texture_cache: dedupe region queries with a picked flag
2026-10-24 04:03:01 +02:00
8dc0d56b7e
common: SlotVector without generations
2026-10-24 03:48:46 +02:00
d7856753e0
shader: walk every resource plan with the x86 SRT walker
2026-10-24 02:57:24 +02:00
f356fa3730
gpu: move the BDA sync queue from MemoryTracker into BufferCache
2026-10-24 01:05:19 +02:00
6aaa533296
gpu: queue GDS release interrupts behind earlier interrupts
2026-10-23 22:22:39 +02:00
dc40478e7b
gpu: deliver RELEASE_MEM interrupts with the slice flush instead of their own
2026-10-23 22:14:55 +02:00
bf5dd62eea
gpu: decode RELEASE_MEM directly from the driver's native packet
2026-10-23 21:11:07 +02:00
227f12ee4b
gpu: remove the PS4-era constant engine, marker NOPs and EVENT_WRITE_EOP/EOS packets
2026-10-23 20:42:41 +02:00
77a8f30758
shader: read S_MEMREALTIME from the host device clock shifted to about 100 MHz
2026-10-23 19:48:53 +02:00
ecc30a1f2d
shader: decode S_FLBIT_I32 and S_FLBIT_I32_I64 with a 4-op signed leading-bit search
2026-10-23 19:48:53 +02:00
38c884e8c1
graphics: keep image heap descriptors of unmapped textures null
2026-10-23 07:17:57 +02:00
27dc7c281f
graphics: keep bounded image heaps resident in a bindless descriptor set
2026-10-23 07:17:57 +02:00
79837b423d
graphics: support compute stores to 2D MSAA images
2026-10-22 22:11:06 +02:00
aafe014d0c
shader: read raw D16 depth bits through kDepth k16UInt image loads
...
Co-authored-by: Artyom Zabroda <artyomzabroda@proton.me >
2026-10-22 22:11:06 +02:00
a358b847c1
graphics: stall waitUntilSafeForRendering in its command processor instead of the GPU thread
2026-10-22 22:11:06 +02:00
a951a91703
spirv: emit OpName only with debug info
2026-10-22 22:11:06 +02:00
86fed10b81
graphics: draw non-indexed and native-fetch indirect draws from GPU-read records
2026-10-22 16:12:20 +02:00
949de19bb0
graphics: draw indexed indirect multi-draws from GPU-read arguments
2026-10-22 16:12:20 +02:00
c513a4a13a
graphics: draw single indexed indirect draws from GPU-read arguments
2026-10-22 16:12:20 +02:00
b54057942d
texture cache: select color-metadata clears on the GPU with conditional rendering
2026-10-22 16:12:20 +02:00
5f5d6effa4
graphics: count DCC/CMASK metadata readbacks in the performance overlay
2026-10-22 16:12:20 +02:00
c5016d9455
shader: support D16 XY and XYZ formatted buffer loads and stores
2026-10-22 05:26:54 +02:00
8502d8a77d
image: drop optional create flags the driver rejects instead of aborting ( #1760 )
...
* image: request extended usage only for storage images
* tests: restore block-texel-view support through the flag check loop order
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-22 03:56:13 +02:00
919fac13d0
shader: read lane 0 in V_READFIRSTLANE when EXEC is zero instead of an undefined lane
2026-10-22 01:20:54 +02:00
11465a5e3c
shader: drop the large-input select before sin and cos since fract already returns zero
2026-10-22 00:44:43 +02:00
09a9654458
shader: compute DPP permute, rotate, mirror and share lanes with bit-field and XOR ops
2026-10-22 00:40:07 +02:00
ce54aa8d14
shader: return the first source when both 64-bit min/max inputs are NaN
2026-10-22 00:28:43 +02:00
1e4ac1371d
shader: return the first source when both float min/max inputs are NaN
2026-10-22 00:00:04 +02:00
da19501889
shader: translate zero-kind branches as the negated nonzero vote
2026-10-21 23:33:30 +02:00
fa32940d14
shader: drop BFM mask bits shifted past bit 31 instead of an out-of-range bit-field insert
2026-10-21 22:59:56 +02:00
aacf15fd0b
shader: write preserved SDWA fields with one bit-field insert and drop duplicate 16-bit masks
2026-10-21 22:52:14 +02:00
10a852c2ac
shader: pack 16-bit lane pairs with one bit-field insert
2026-10-21 22:46:04 +02:00
6e5167598e
shader: compute add-with-carry with compares and remove IAddCarry32
2026-10-21 22:28:11 +02:00
286481889f
shader: emit float min/max as host instructions on AMD GPUs ( #1761 )
...
* shader: emit float min/max as host instructions on AMD GPUs
V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.
In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.
Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.
Developed with AI assistance (Claude Code).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: gate host float min/max on RADV and check the emitted instructions
* shader: drop float controls 2 from host float min/max
* shader: drop the float min/max env override and atomic flag
* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device
* shader: enable host float min/max on AMD GPUs
---------
Co-authored-by: arda <ardaeska@gmail.com >
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 21:36:08 +02:00
3c4124dafa
shader: emit F32 min/max as exact compare-selects, MED3 with one max and saturate as NClamp
2026-10-20 23:36:26 +02:00
1ce663b5a9
shader: lower HS neighbour LDS reads, control-point output read-back, looped HS reflection and integer partitioning
...
Co-authored-by: NeySlim <4509984+NeySlim@users.noreply.github.com >
2026-10-20 22:18:00 +02:00
f3e01aaf1e
tests: cover tessellation patch constants, predicated mul24 addresses, and forward-branch joins
2026-10-20 15:21:19 +02:00
fde0b98e69
gpu: preserve zero-stride buffer fetch payloads
2026-10-19 12:23:43 +02:00
nmzik