Commit Graph

239 Commits

Author SHA1 Message Date
nmzik 6123419437 shader: skip full DPP row and bank masks and test partial ones with one bit extract 2026-10-22 00:35:09 +02:00
nmzik 8177969f33 shader: branch to the pixel kill on the inverted targets instead of negating the condition 2026-10-22 00:33:07 +02:00
nmzik ce54aa8d14 shader: return the first source when both 64-bit min/max inputs are NaN 2026-10-22 00:28:43 +02:00
nmzik 3bb09ed2a4 shader: clamp before float-to-int conversion and drop the redundant truncate 2026-10-22 00:26:40 +02:00
nmzik 1e4ac1371d shader: return the first source when both float min/max inputs are NaN 2026-10-22 00:00:04 +02:00
nmzik 93071ebdf8 shader: drop the denormal flush before exp2 2026-10-21 23:33:42 +02:00
nmzik 3a842e1a6b shader: flush FP32 denormals with a float compare and multiply instead of bit masks 2026-10-21 23:33:42 +02:00
nmzik 0f7d112545 shader: emit constant-true guarded blocks inline and fold immediate constant-buffer indices 2026-10-21 23:27:04 +02:00
nmzik 10a852c2ac shader: pack 16-bit lane pairs with one bit-field insert 2026-10-21 22:46:04 +02:00
nmzik 4a1440197f shader: share one find-first-bit lowering for S_FF0/FF1/FLBIT_I32_B64 and remove FindUMsb64 2026-10-21 22:39:34 +02:00
nmzik 6e5167598e shader: compute add-with-carry with compares and remove IAddCarry32 2026-10-21 22:28:11 +02:00
nmzik c571d8ed5a shader: remove IR opcodes and IREmitter helpers that nothing produces 2026-10-21 22:19:26 +02:00
Arda Sahin 286481889f shader: emit float min/max as host instructions on AMD GPUs (#1761)
* shader: emit float min/max as host instructions on AMD GPUs

V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.

In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.

Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.

Developed with AI assistance (Claude Code).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* shader: gate host float min/max on RADV and check the emitted instructions

* shader: drop float controls 2 from host float min/max

* shader: drop the float min/max env override and atomic flag

* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device

* shader: enable host float min/max on AMD GPUs

---------

Co-authored-by: arda <ardaeska@gmail.com>
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Co-authored-by: nmzik <Nmzik@mail.ru>
2026-10-21 21:36:08 +02:00
nmzik ea1b032c59 shader: drop the unread F32Class bits and the per-pass HS reflection counter reset 2026-10-20 23:54:32 +02:00
nmzik 3c4124dafa shader: emit F32 min/max as exact compare-selects, MED3 with one max and saturate as NClamp 2026-10-20 23:36:26 +02:00
nmzik 8cc5f5364a shader: share SMEM load results across emulated wave64 halves 2026-10-20 22:32:48 +02:00
nmzik 1ce663b5a9 shader: lower HS neighbour LDS reads, control-point output read-back, looped HS reflection and integer partitioning
Co-authored-by: NeySlim <4509984+NeySlim@users.noreply.github.com>
2026-10-20 22:18:00 +02:00
Mr. Big Britches 0957f088ad shader: reflect HS patch constants and lower TES patch inputs through predicated addresses 2026-10-20 15:21:19 +02:00
Mr. Big Britches f0e462a8a2 shader: allocate split-wave dispatcher spill IDs in program order 2026-10-20 15:21:19 +02:00
Mr. Big Britches feed075a9f gpu: implement PA_CL_UCP user clip planes through draw push constants 2026-10-20 15:21:19 +02:00
nmzik f186b35706 shader: drop null checks on the stage input info pointers 2026-10-20 03:22:40 +02:00
0xcrstn fa8216c4d9 shader: size per-thread LDS emulation by the guest LDS allocation 2026-10-20 02:51:27 +02:00
nmzik defb2f11d3 Share median classifications and preserve RDNA2 signed-zero selection 2026-10-19 02:34:25 +02:00
nmzik 09c993dfe0 shader: query dimensions through shared indirect image selection 2026-10-19 02:34:25 +02:00
nmzik ac3711ce7c shader: select the primary mip for linear explicit-LOD gathers 2026-10-19 02:34:24 +02:00
nmzik 8639e0de81 shader: share indirect image accesses by type and guard emitted size 2026-10-18 20:16:49 +02:00
nmzik 22ef16a044 shader: implement PS5 vector data cache invalidation 2026-10-18 15:57:14 +02:00
nmzik 9f88043ebe shader: use compact integer RTZ half conversion 2026-10-17 12:23:12 +02:00
nmzik d1fe1324c8 shader: keep coherent 64bit atomic 2026-10-17 07:52:20 +02:00
Nawid3333 e93b4b0378 shader: support returning 32-bit LDS compare-exchange (DS_CMPST_RTN_B32) (#1578)
* shader: support DS_CMPST_RTN_B32

Assassin's Creed Valhalla (PPSA01490, #281) stops on DS opcode 0x30 in a
compute shader. DS compares DATA and stores DATA2, the opposite of
BUFFER_ATOMIC_CMPSWAP, so the 32-bit atomic path swaps the two for this
opcode, as the 64-bit form does.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* shader: reject unsupported GDS compare-store variant

---------

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Co-authored-by: nmzik <Nmzik@mail.ru>
2026-10-17 04:37:16 +02:00
Çağatay Güçlü 02ead0e2e1 shader: 64-bit buffer atomic add (BUFFER_ATOMIC_ADD_X2) 2026-10-17 04:09:54 +02:00
NeySlim 4f1f3b1bb3 shader: make the f32 clamp modifier turn NaN into 0 2026-10-17 04:09:53 +02:00
nmzik d01633e18e Revert "Fix scalar buffer reads across sparse guest mappings"
This reverts commit d7974dc763.
2026-10-16 19:13:36 +02:00
nmzik d7974dc763 Fix scalar buffer reads across sparse guest mappings 2026-10-16 18:20:31 +02:00
shadowbeat070 57b161019d shader: honor front-face input format 2026-10-16 12:57:27 +02:00
AN0DIN 83db2efec3 shader: pack v_cvt_pkrtz_f16_f32 with the native half conversion (GTA V) (#1520)
* shader: pack v_cvt_pkrtz_f16_f32 with the native half conversion

The round-toward-zero pack was emulated with integer operations: about 20 to 30 operations
per half. GTA V uses it in 613 of its 656 pixel shaders, about 16 times in each G-buffer
pixel shader.

The pair is now packed with PackHalf2x16, unpacked again, and each half whose magnitude
exceeds its input's takes one unit off. Half signs and magnitudes are separate, so that is
the next value toward zero, whatever rounding the native conversion uses as long as it
returns one of the two neighbours. Same bits as before for every finite input and infinity;
a NaN stays a NaN. Checked against the old code on 2 million values on the CPU, and on an
Apple M5 GPU through Metal (400 000 values, subnormals included, safe and fast math).

GTA V on an Apple M5 (MoltenVK), 1080p, fixed script camera, three places, A B B A between
launches: -1.7 to -2.8 ms per frame (+4 to +6 %).

Scope: generic
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* shader: remove half-pack commentary and unused shift helper

---------

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Co-authored-by: nmzik <Nmzik@mail.ru>
2026-10-16 02:56:35 +02:00
nmzik f7226ca7dc graphics: emit PS5 register object and primitive IDs to RT7 2026-10-15 22:28:01 +02:00
nmzik b4406b0467 graphics: render packed 11-11-10 UNorm targets with exact rounding
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik fb213e8ae5 shader: share packed color component encoding 2026-10-15 22:28:01 +02:00
nmzik 1d3fd07fe6 shader: share indirect buffer format geometry lookup 2026-10-15 22:28:01 +02:00
nmzik bb2d6dbeb3 shader: share scalar condition results with direct subgroup votes
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-15 22:28:01 +02:00
nmzik 50844badbf shader: map debug SPIR-V blocks to native RDNA2 PCs 2026-10-15 22:28:01 +02:00
nmzik c1f6838e40 shader: share repeated raw indirect buffer load bodies 2026-10-15 22:28:01 +02:00
nmzik 8b81f665a2 shader: separate indirect buffer candidates from tracked root limits
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 21:19:38 +02:00
nmzik 1039c54f5d shader: share indirect buffer array access after an empty root
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 21:17:44 +02:00
nmzik b24ce3440d shader: track buffer liveness and offsets by resource count
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 21:11:14 +02:00
nmzik 4843d8d942 shader: support packed D16 XYZW formatted buffer stores
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 19:35:08 +02:00
nmzik 7468e4f60a shader: share descriptor dispatch for scalar and wide buffer stores 2026-10-14 19:01:14 +02:00
nmzik b6da068313 shader: preserve typed candidates for unfiltered indirect image access
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 18:57:26 +02:00
nmzik 127cf8d46f shader: route image stores through shared indirect descriptor access
Co-authored-by: fxpw <fxpw@outlook.com>
2026-10-14 18:39:40 +02:00