d1fe1324c8
shader: keep coherent 64bit atomic
2026-10-17 07:52:20 +02:00
83db2efec3
shader: pack v_cvt_pkrtz_f16_f32 with the native half conversion (GTA V) ( #1520 )
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* shader: pack v_cvt_pkrtz_f16_f32 with the native half conversion
The round-toward-zero pack was emulated with integer operations: about 20 to 30 operations
per half. GTA V uses it in 613 of its 656 pixel shaders, about 16 times in each G-buffer
pixel shader.
The pair is now packed with PackHalf2x16, unpacked again, and each half whose magnitude
exceeds its input's takes one unit off. Half signs and magnitudes are separate, so that is
the next value toward zero, whatever rounding the native conversion uses as long as it
returns one of the two neighbours. Same bits as before for every finite input and infinity;
a NaN stays a NaN. Checked against the old code on 2 million values on the CPU, and on an
Apple M5 GPU through Metal (400 000 values, subnormals included, safe and fast math).
GTA V on an Apple M5 (MoltenVK), 1080p, fixed script camera, three places, A B B A between
launches: -1.7 to -2.8 ms per frame (+4 to +6 %).
Scope: generic
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: remove half-pack commentary and unused shift helper
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Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-16 02:56:35 +02:00
f7226ca7dc
graphics: emit PS5 register object and primitive IDs to RT7
2026-10-15 22:28:01 +02:00
b4406b0467
graphics: render packed 11-11-10 UNorm targets with exact rounding
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
fb213e8ae5
shader: share packed color component encoding
2026-10-15 22:28:01 +02:00
1d3fd07fe6
shader: share indirect buffer format geometry lookup
2026-10-15 22:28:01 +02:00
50844badbf
shader: map debug SPIR-V blocks to native RDNA2 PCs
2026-10-15 22:28:01 +02:00
c1f6838e40
shader: share repeated raw indirect buffer load bodies
2026-10-15 22:28:01 +02:00
1039c54f5d
shader: share indirect buffer array access after an empty root
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 21:17:44 +02:00
b24ce3440d
shader: track buffer liveness and offsets by resource count
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 21:11:14 +02:00
127cf8d46f
shader: route image stores through shared indirect descriptor access
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 18:39:40 +02:00
150bcb06a9
shader: share runtime buffer format conversion across loads
2026-10-14 14:29:40 +02:00
26d326d1b0
shader: share bounded record descriptors for packed loads and byte stores
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 05:07:24 +02:00
c11254a996
shader: share format conversion for packed normalized image stores
2026-10-13 21:27:07 +00:00
e2c8b61de6
shader: remove unreachable mixed image specialization paths
2026-10-13 21:27:07 +00:00
f01a3750d4
shader: validate indirect image operands at each typed access
2026-10-13 21:27:07 +00:00
460a196fca
shader: emit dynamic sample offsets with the enabled maintenance8 feature
2026-10-13 21:27:07 +00:00
fd66f580b4
shader: resolve packed buffer selectors with shared indexed stores
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-13 21:27:07 +00:00
8c81386568
shader: share finite descriptor planning with GPU-selected inline samplers
2026-10-09 15:06:39 +00:00
ee4dd90649
shader: emit native integer operations and remove signedness casts
2026-10-09 02:54:21 +02:00
46997dfc7a
shader: retain resource type IDs in SPIR-V emission state
2026-10-09 01:55:50 +02:00
e1ac893a0c
shader: collect usage once and emit descriptor slots directly
2026-10-09 02:17:38 +04:00
52dbc724f8
shader: store SPIR-V definitions directly in IR nodes
2026-10-09 01:40:41 +04:00
5b826c6e4a
shader: emit native 64-bit operations where compatible
2026-10-05 20:41:03 +04:00
7a0e1dafd7
shader: classify native half values with shared operand decoding
2026-10-05 18:39:31 +04:00
e85279ea7b
shader: correct DS float min/max operands and special values
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-05 04:11:48 +04:00
b0bbaef1eb
gpu: store large compute shared memory in device buffers
2026-10-05 02:24:51 +04:00
39248a1f87
shader: emit per-vertex mesh clip and cull distances
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Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
c3f4962715
shader: use native narrow storage for byte-aligned PS5 buffers
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Co-authored-by: MehmetCambaz <mcambaz18@gmail.com >
2026-10-04 18:39:34 +04:00
843b577880
shader: resolve bounded GPU material keys through sampled image arrays
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Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
2026-10-04 18:39:34 +04:00
a55a28380d
shader: decode GPU-selected formatted buffer loads with native bounds
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Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
2026-10-04 18:39:34 +04:00
f58014ff0e
shader: preserve wave-wide vector-store completion before publication
2026-10-04 18:39:34 +04:00
429d0af62b
shader: bind bounded GPU-selected buffer store destinations
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-04 18:39:34 +04:00
bd611bfe15
Honor explicit gather LOD with shared image mip selection
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Co-authored-by: YuhiAida <21134775+YuhiAida@users.noreply.github.com >
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com >
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-03 14:19:33 +04:00
b3e419ff11
shader: implement 32-bit RDNA2 IMAGE_ATOMIC_CMPSWAP ( #952 )
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* shader: implement 32-bit RDNA2 image atomic compare-and-swap
* shader: share atomic emission and correct image barriers
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Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-02 01:15:53 +04:00
7101741637
Cache SPIR-V arithmetic types lazily in existing emitters
2026-10-02 00:53:51 +04:00
337f432016
shader: execute PS5 BVH intersections and local FLAT stacks
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Jean-Philippe <github@meunier.jp >
2026-10-02 00:51:15 +04:00
6799ecbc5b
shader: add native 64-bit LDS OR with shared typed storage views
2026-09-29 19:13:33 +04:00
16b83a034c
Shader: execute RDNA2 FP64 shadow arithmetic and log denorm limits
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Shader: disable FP64 denorm preservation controls for now
2026-09-26 15:15:35 +04:00
dc9280d75d
shader: add GLC/DLC buffer cache policy support
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Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
8a5e5c5476
Fold buffer address identities and remove empty predicates
2026-09-23 15:41:02 +04:00
bfc8cd0e0b
shader: DPP8 moves
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Co-authored-by: foufouadi <attar.foued@gmail.com >
Co-authored-by: fxpw <fxpw@outlook.com >
2026-09-18 09:11:55 +04:00
5dc644edb4
clean up graphics helpers
2026-09-17 20:35:36 +04:00
86414760e6
Cull zero homogeneous vertex positions before rasterization
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Fix Playroom top right artifact on Nvidia by clipping zero-position vertices.
2026-09-15 11:24:05 +04:00
87971a28f5
gpu: isolate tessellation analysis and SPIR-V emission
2026-09-14 06:58:32 +04:00
7516068662
gpu: compile RDNA2 tessellation through native LS HS and TES stages
2026-09-14 06:58:32 +04:00
1208d22547
Fix Windows Clang SPIR-V serialization with typed operands
2026-09-12 13:08:23 +02:00
2d37634ee9
shader: construct SPIR-V module variables in one place
2026-09-12 13:42:15 +04:00
20e57994cf
shader: reuse native emitters and simplify memory dispatch
2026-09-12 13:42:15 +04:00
59ef88c959
shader: generate SPIR-V dispatch and marshal handler arguments
2026-09-12 13:42:15 +04:00
nmzik