8502d8a77d
image: drop optional create flags the driver rejects instead of aborting ( #1760 )
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* image: request extended usage only for storage images
* tests: restore block-texel-view support through the flag check loop order
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Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-22 03:56:13 +02:00
cb8042c5aa
launcher: compress game folders to ZAR
2026-10-22 03:35:38 +02:00
b46eeb7866
audio: stop AudioOut2 contexts from stalling each other (PPSA09809) ( #1745 )
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audio: submit AudioOut2 pushes outside the state mutex so contexts stop stalling each other
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-22 02:52:11 +02:00
05694abad5
audio: play dataless and streamed NGS2 PCM waveform blocks for Oricru ( #1787 )
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ngs2: stream PCM waveform blocks by byte like ATRAC9 so blocks may hold fewer frames than their duration
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-22 02:09:04 +02:00
919fac13d0
shader: read lane 0 in V_READFIRSTLANE when EXEC is zero instead of an undefined lane
2026-10-22 01:20:54 +02:00
a52d1ed4e2
shader: drop the 64-bit min/max NaN-lhs select the ordered compare already covers
2026-10-22 01:09:09 +02:00
2b37dee2b7
shader: track possible bits through bit-field inserts in resource tracking
2026-10-22 01:08:07 +02:00
a3aece2762
shader: check the DPP source lane bound only for row shifts
2026-10-22 01:02:38 +02:00
64186404a3
shader: load the DPP lane id once for both partial write masks
2026-10-22 01:01:38 +02:00
11465a5e3c
shader: drop the large-input select before sin and cos since fract already returns zero
2026-10-22 00:44:43 +02:00
09a9654458
shader: compute DPP permute, rotate, mirror and share lanes with bit-field and XOR ops
2026-10-22 00:40:07 +02:00
6123419437
shader: skip full DPP row and bank masks and test partial ones with one bit extract
2026-10-22 00:35:09 +02:00
8177969f33
shader: branch to the pixel kill on the inverted targets instead of negating the condition
2026-10-22 00:33:07 +02:00
6ee2ef8715
shader: insert the V_CVT_PK_U8_F32 byte with one bit-field insert
2026-10-22 00:31:52 +02:00
9e4234cdbe
shader: extract the V_CVT_F32_UBYTE source byte with one bit-field extract
2026-10-22 00:30:39 +02:00
ce54aa8d14
shader: return the first source when both 64-bit min/max inputs are NaN
2026-10-22 00:28:43 +02:00
2d00e13bf3
shader: rely on the saturating float-to-int conversion instead of re-saturating in the translator
2026-10-22 00:26:40 +02:00
3bb09ed2a4
shader: clamp before float-to-int conversion and drop the redundant truncate
2026-10-22 00:26:40 +02:00
1e4ac1371d
shader: return the first source when both float min/max inputs are NaN
2026-10-22 00:00:04 +02:00
9c39062d3e
shader: double the cube major axis once after selecting the face
2026-10-21 23:56:13 +02:00
93071ebdf8
shader: drop the denormal flush before exp2
2026-10-21 23:33:42 +02:00
3a842e1a6b
shader: flush FP32 denormals with a float compare and multiply instead of bit masks
2026-10-21 23:33:42 +02:00
da19501889
shader: translate zero-kind branches as the negated nonzero vote
2026-10-21 23:33:30 +02:00
0f7d112545
shader: emit constant-true guarded blocks inline and fold immediate constant-buffer indices
2026-10-21 23:27:04 +02:00
ae47ac26e7
shader: compute scalar signed-overflow SCC with compares instead of XOR masks
2026-10-21 23:27:04 +02:00
330d373dc6
launcher: add icon and docs logo
2026-10-21 23:27:04 +02:00
7c40dbc36c
shader: build the S_BFE_U64 mask from clamped halves and remove RightMask64
2026-10-21 23:16:17 +02:00
0cdc5c1224
shader: build the V_MBCNT lanes-below mask with the shared right-mask helper
2026-10-21 23:11:26 +02:00
fa32940d14
shader: drop BFM mask bits shifted past bit 31 instead of an out-of-range bit-field insert
2026-10-21 22:59:56 +02:00
2862ad5b25
shader: compute scalar signed-overflow and shift-add carry SCC with fewer ops
2026-10-21 22:56:21 +02:00
aacf15fd0b
shader: write preserved SDWA fields with one bit-field insert and drop duplicate 16-bit masks
2026-10-21 22:52:14 +02:00
10a852c2ac
shader: pack 16-bit lane pairs with one bit-field insert
2026-10-21 22:46:04 +02:00
4a1440197f
shader: share one find-first-bit lowering for S_FF0/FF1/FLBIT_I32_B64 and remove FindUMsb64
2026-10-21 22:39:34 +02:00
6e5167598e
shader: compute add-with-carry with compares and remove IAddCarry32
2026-10-21 22:28:11 +02:00
c571d8ed5a
shader: remove IR opcodes and IREmitter helpers that nothing produces
2026-10-21 22:19:26 +02:00
286481889f
shader: emit float min/max as host instructions on AMD GPUs ( #1761 )
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* shader: emit float min/max as host instructions on AMD GPUs
V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.
In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.
Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.
Developed with AI assistance (Claude Code).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: gate host float min/max on RADV and check the emitted instructions
* shader: drop float controls 2 from host float min/max
* shader: drop the float min/max env override and atomic flag
* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device
* shader: enable host float min/max on AMD GPUs
---------
Co-authored-by: arda <ardaeska@gmail.com >
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 21:36:08 +02:00
c07ad621f2
graphics: write small GPU-written tiled images back to guest memory behind --readback-tiled-images
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Co-authored-by: Dimitar Vagalinski <275970482+overlordxrz-source@users.noreply.github.com >
Co-authored-by: Mr. Big Britches <111622360+MrBigBritches@users.noreply.github.com >
2026-10-21 20:55:02 +02:00
80932f8da1
Remove leftover update workspace folders on launcher startup ( #1782 )
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* Remove leftover update workspace folders on launcher startup
Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com >
* Skip recently active update workspaces during cleanup
Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com >
* Keep update workspaces for an hour before cleanup so Windows downloads are not removed
---------
Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 20:43:30 +02:00
f0e55803ba
Add CMakeUserPresets.json to .gitignore ( #1766 )
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Add CMakeUserPresets.json to the .gitignore
2026-10-21 20:41:03 +02:00
ca6a7b88ce
launcher: add Enable all / Disable all to the cheats dialog ( #1773 )
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launcher: add Enable all / Disable all buttons to the cheats dialog
Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com >
2026-10-21 20:34:59 +02:00
13b291f998
gpu: honour DB_ALPHA_TO_MASK as alpha-to-coverage and keep its depth writes behind the shader
2026-10-21 19:17:50 +02:00
2944d126b3
audio: implement sceAudioOutGetSystemState
2026-10-21 19:17:50 +02:00
7b7294aa03
gpu: drop attachments whose sample count differs from the raster when a draw mixes MSAA and single-sample targets
2026-10-21 19:17:50 +02:00
4644c52927
graphics: initialize BDA tables before first buffer registration
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Co-authored-by: Leandro Bras <shadowgaming.7@gmail.com >
2026-10-21 05:48:13 +02:00
4bb4be50b9
agc: remove count-limited logging and register trace
2026-10-21 05:48:13 +02:00
be9e13915d
log: format LOGF output out of line so small guest fiber stacks do not reserve it
2026-10-21 05:48:13 +02:00
68d0ba5a81
shader: bound scalar-read overlap checks by the bytes fixed-offset buffer writes reach
2026-10-21 05:48:13 +02:00
70668fbd98
gpu: drop global barriers for PM4 flush events and releases, ordering buffer-writing draws like dispatches
2026-10-21 02:02:25 +02:00
ea1b032c59
shader: drop the unread F32Class bits and the per-pass HS reflection counter reset
2026-10-20 23:54:32 +02:00
3c4124dafa
shader: emit F32 min/max as exact compare-selects, MED3 with one max and saturate as NClamp
2026-10-20 23:36:26 +02:00
Arda Sahin