27dc7c281f
graphics: keep bounded image heaps resident in a bindless descriptor set
2026-10-23 07:17:57 +02:00
a951a91703
spirv: emit OpName only with debug info
2026-10-22 22:11:06 +02:00
286481889f
shader: emit float min/max as host instructions on AMD GPUs ( #1761 )
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* shader: emit float min/max as host instructions on AMD GPUs
V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.
In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.
Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.
Developed with AI assistance (Claude Code).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: gate host float min/max on RADV and check the emitted instructions
* shader: drop float controls 2 from host float min/max
* shader: drop the float min/max env override and atomic flag
* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device
* shader: enable host float min/max on AMD GPUs
---------
Co-authored-by: arda <ardaeska@gmail.com >
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 21:36:08 +02:00
f186b35706
shader: drop null checks on the stage input info pointers
2026-10-20 03:22:40 +02:00
d01633e18e
Revert "Fix scalar buffer reads across sparse guest mappings"
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This reverts commit d7974dc763
2026-10-16 19:13:36 +02:00
d7974dc763
Fix scalar buffer reads across sparse guest mappings
2026-10-16 18:20:31 +02:00
50844badbf
shader: map debug SPIR-V blocks to native RDNA2 PCs
2026-10-15 22:28:01 +02:00
8b81f665a2
shader: separate indirect buffer candidates from tracked root limits
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 21:19:38 +02:00
b24ce3440d
shader: track buffer liveness and offsets by resource count
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 21:11:14 +02:00
26d326d1b0
shader: share bounded record descriptors for packed loads and byte stores
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 05:07:24 +02:00
460a196fca
shader: emit dynamic sample offsets with the enabled maintenance8 feature
2026-10-13 21:27:07 +00:00
e1ac893a0c
shader: collect usage once and emit descriptor slots directly
2026-10-09 02:17:38 +04:00
a8beac190f
shader: evaluate scalar branch decisions across the complete guest wave
2026-10-07 21:17:35 +04:00
9caec9f2c8
shader: preserve RDNA2 DLC coherence for flat address loads
2026-10-06 14:53:17 +04:00
b0bbaef1eb
gpu: store large compute shared memory in device buffers
2026-10-05 02:24:51 +04:00
c3f4962715
shader: use native narrow storage for byte-aligned PS5 buffers
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Co-authored-by: MehmetCambaz <mcambaz18@gmail.com >
2026-10-04 18:39:34 +04:00
c17fa5b936
shader: implement RDNA2 DS forward lane permute
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
b4d32394b6
shader: keep GPU-derived scalar resource reads on the GPU
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
2026-10-04 18:39:34 +04:00
e4aca7a60b
shader: initialize EXEC from requested dispatch thread extents
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Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
2026-10-04 18:39:34 +04:00
f58014ff0e
shader: preserve wave-wide vector-store completion before publication
2026-10-04 18:39:34 +04:00
bd611bfe15
Honor explicit gather LOD with shared image mip selection
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Co-authored-by: YuhiAida <21134775+YuhiAida@users.noreply.github.com >
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com >
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-03 14:19:33 +04:00
0d0b215fab
shader: port 64-bit ALU and atomic opcodes
2026-10-02 00:51:15 +04:00
337f432016
shader: execute PS5 BVH intersections and local FLAT stacks
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Jean-Philippe <github@meunier.jp >
2026-10-02 00:51:15 +04:00
6799ecbc5b
shader: add native 64-bit LDS OR with shared typed storage views
2026-09-29 19:13:33 +04:00
0791f921f6
UFC 5 in-game ( #883 )
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* shader: release descriptor dependencies
* shader: simplify shared-exit control flow
* shader: fix scalar memory loads
* shader: fix LDS counter bounds
* renderer: skip inactive pixel shaders
* shader: respect FP32 mode in comparisons
* renderer: fix sampler border colors
* shader: resolve descriptors from control flow
* shader: resolve descriptors before resource planning
* shader: handle scalar guards for image bounds
* shader: handle reduced guards for image loops
* shader: fix wave guards and material indices
* shader: preserve scalar buffer offset alignment and carry
* shader: prove masked loop bounds across iteration transitions
* shader: preserve source and IR before resource tracking failures
* shader: track material keys selected from active lanes
* shader: remove obsolete post-dominator analysis
* shader: follow bounds guards through control-flow joins
2026-09-28 16:03:05 +04:00
bec67b7863
Fix HITMAN 3 boot, layered presentation, and socket imports ( #851 )
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* videoout: synchronize layered flips with premultiplied composition
* shader: support unsigned FFBH subword sources
* shader: apply cube-face result scaling
* shader: prune buffer reads proven out of bounds
* net: implement send and receive exports with shared socket handling
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-27 02:13:30 +04:00
16b83a034c
Shader: execute RDNA2 FP64 shadow arithmetic and log denorm limits
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Shader: disable FP64 denorm preservation controls for now
2026-09-26 15:15:35 +04:00
dc9280d75d
shader: add GLC/DLC buffer cache policy support
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Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
b2a80a3a96
Resolve GPU-selected raw buffer descriptors through shared RDNA2 addressing
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Co-authored-by: Bipin <87369440+bipinkrish@users.noreply.github.com >
2026-09-22 11:38:50 +04:00
7516068662
gpu: compile RDNA2 tessellation through native LS HS and TES stages
2026-09-14 06:58:32 +04:00
2d37634ee9
shader: construct SPIR-V module variables in one place
2026-09-12 13:42:15 +04:00
1d1f00bdef
shader: use Khronos definitions and simplify compiler ownership
2026-09-12 13:42:15 +04:00
2b3993a595
shader: share emitter helpers
2026-09-08 21:26:59 +04:00
cd62693792
shader: share control flow labels
2026-09-08 21:26:59 +04:00
3213934d42
shader: run merged geometry stages as mesh shaders
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Co-authored-by: Brandon Strong <brandostrong@gmail.com >
Co-authored-by: fxpw <fxpw@outlook.com >
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-09-05 08:32:23 +04:00
b3c8f91a84
graphics: implement RDNA2 buffer atomic swap x2
2026-09-03 10:17:04 +02:00
858c18468b
graphics: implement RDNA2 buffer atomic OR x2
2026-09-03 05:39:05 +02:00
98200fed19
shader: rework resource specialization and optimize pipeline caching
2026-09-03 03:04:17 +02:00
af8aecfdde
shader: remove recompiler error-string propagation
2026-08-31 05:31:41 +04:00
5bd447d2a2
shader: implement DS_BPERMUTE_B32
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Co-authored-by: Techx3 <56268269+Techx3@users.noreply.github.com >
2026-08-29 19:23:19 +04:00
e738535294
graphics: add RDNA2 FLAT BDA buffer cache and faults
2026-08-27 03:45:41 +02:00
ffa69d48de
shader: remove second IR layer
2026-08-26 08:49:39 +02:00
bad6726f5e
Rewrite descriptor bindings and unify graphics push constants
2026-08-21 22:28:10 +02:00
49ea1680f8
graphics: use per-invocation shader masks
2026-08-21 08:03:22 +02:00
d0a4c908a1
shader: align address-memory buffer bindings
2026-08-21 03:32:49 +02:00
56a15c2036
Implement RDNA2 per-invocation scratch memory
2026-08-21 03:32:47 +02:00
85cf965d54
refactor(shader): centralize typed resource metadata
2026-08-21 03:32:47 +02:00
c236ba713d
refactor(shader): preserve native wide shared operations
2026-08-21 03:32:47 +02:00
3ea2099245
refactor(shader): simplify buffer access emission
2026-08-21 03:32:47 +02:00
d34e30d892
refactor(shader): emit SPIR-V declarations on demand
2026-08-21 03:32:47 +02:00
nmzik