286481889f
shader: emit float min/max as host instructions on AMD GPUs ( #1761 )
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* shader: emit float min/max as host instructions on AMD GPUs
V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.
In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.
Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.
Developed with AI assistance (Claude Code).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: gate host float min/max on RADV and check the emitted instructions
* shader: drop float controls 2 from host float min/max
* shader: drop the float min/max env override and atomic flag
* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device
* shader: enable host float min/max on AMD GPUs
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Co-authored-by: arda <ardaeska@gmail.com >
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 21:36:08 +02:00
13b291f998
gpu: honour DB_ALPHA_TO_MASK as alpha-to-coverage and keep its depth writes behind the shader
2026-10-21 19:17:50 +02:00
68d0ba5a81
shader: bound scalar-read overlap checks by the bytes fixed-offset buffer writes reach
2026-10-21 05:48:13 +02:00
70668fbd98
gpu: drop global barriers for PM4 flush events and releases, ordering buffer-writing draws like dispatches
2026-10-21 02:02:25 +02:00
8843291506
gpu: accept any T# perf_mod on storage textures through a shared canonical encoding check
2026-10-20 15:21:19 +02:00
feed075a9f
gpu: implement PA_CL_UCP user clip planes through draw push constants
2026-10-20 15:21:19 +02:00
cd4eab9d65
gpu: clamp resolved buffer ranges to storage buffer limits
2026-10-19 13:53:18 +02:00
fde0b98e69
gpu: preserve zero-stride buffer fetch payloads
2026-10-19 12:23:43 +02:00
d4465faa79
gpu: preserve ordered-append command order
2026-10-19 11:46:39 +02:00
e5f0ee7fc2
gpu: preserve finite buffer descriptors across sparse PRT holes
2026-10-19 05:26:41 +02:00
2c730e58ea
revert HTile lifetime changes and opt-in ZMask support
2026-10-19 05:04:56 +02:00
cad6aafdc5
shader: detect and loudly skip unsupported GPU-buffer callables
2026-10-19 05:04:56 +02:00
ab8566591f
shader: link multiple compute helpers without synthetic return loops
2026-10-19 02:34:25 +02:00
b2d3ce6dfc
shader: size expanded sampler bindings independently of native roots
2026-10-19 02:34:25 +02:00
37df7f3278
Show pipeline cache sizes in MB and remove obsolete texture folder cleanup
2026-10-18 03:57:45 +02:00
763d3be3a9
graphics: add opt-in ZMask support and launcher rendering options
2026-10-17 17:50:02 +02:00
6aa3846fb2
feat: add an in-game performance panel ( #1090 )
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Add in-game performance panel
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-17 14:47:51 +02:00
d58aefde49
renderer: reduce synchronization and allocation overhead
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Performance changes from #1495 :
- Sync changed BDA ranges instead of scanning all mappings.
- Let VMA suballocate BDA buffers.
- Remove the renderer lock from presentation.
- Keep compatible pipeline caches across builds.
- Fold masked shifts that always produce zero.
2026-10-16 17:18:49 +02:00
f7226ca7dc
graphics: emit PS5 register object and primitive IDs to RT7
2026-10-15 22:28:01 +02:00
959bee4799
graphics: checkpoint live Vulkan pipeline cache after new compilations
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
b4406b0467
graphics: render packed 11-11-10 UNorm targets with exact rounding
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
50844badbf
shader: map debug SPIR-V blocks to native RDNA2 PCs
2026-10-15 22:28:01 +02:00
8b81f665a2
shader: separate indirect buffer candidates from tracked root limits
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 21:19:38 +02:00
ceccd746d8
shader: resolve workgroup-selected descriptor prefixes from dispatch arguments
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 20:29:48 +02:00
892e70c8a1
graphics: bind unbound textures as native null descriptors
2026-10-14 17:56:47 +02:00
8c7fe539b8
graphics: represent rebased contiguous mip-tail texture views
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 15:56:45 +02:00
c88f05f7b5
graphics: share signed storage conversion and support R16 image writes
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 15:36:29 +02:00
56738aa4e1
shader: sample packed normalized images with one bilinear gather
2026-10-13 21:27:07 +00:00
c11254a996
shader: share format conversion for packed normalized image stores
2026-10-13 21:27:07 +00:00
aec8c88755
graphics: support signed 32-bit image atomic descriptors
2026-10-13 21:27:07 +00:00
460a196fca
shader: emit dynamic sample offsets with the enabled maintenance8 feature
2026-10-13 21:27:07 +00:00
8f7d745383
graphics: simplify image usage and dirty state
2026-10-13 21:27:07 +00:00
f28c0fccb2
texture: preserve guest DCC metadata for comparison depth aliases
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Co-authored-by: netwarex <mail@pety.me >
2026-10-11 18:53:01 +02:00
5559cfcbb2
renderer: optimize tiling and reuse centralized image layouts
2026-10-10 03:27:13 +02:00
3e9f88bf79
shader: isolate SWAPPC work from ordinary shader paths
2026-10-09 17:27:07 +02:00
1818aae562
shader: link scalar leaf calls only for SWAPPC programs
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Co-authored-by: Behzad <behzadkhan1736@gmail.com >
2026-10-09 15:06:39 +00:00
97fda7b10f
renderer: bind prepared buffer descriptors without copying
2026-10-09 01:49:18 +02:00
e1ac893a0c
shader: collect usage once and emit descriptor slots directly
2026-10-09 02:17:38 +04:00
b38b7454a6
Preserve vertex export locations for mixed pixel interpolation
2026-10-08 22:05:53 +04:00
470669c677
graphics: make raw image synchronization an opt-in setting
2026-10-07 21:17:35 +04:00
743fdc6990
graphics: synchronize raw storage reads with GPU image aliases
2026-10-07 21:17:35 +04:00
e5dcfdb87b
graphics: bound unbounded buffer reads and writes ( #1066 )
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Co-authored-by: João Lobo <joaodlobo@gmail.com >
2026-10-06 00:35:02 +04:00
984010227f
graphics: make depth bounds dynamic to reuse pipelines
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Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
2026-10-06 00:35:02 +04:00
94e7d239dd
gpu: fix zero-source alpha blending on swizzled targets
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Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
96011cc5c9
gpu: share pipelines when color and alpha blend equations match
2026-10-05 02:24:51 +04:00
b0bbaef1eb
gpu: store large compute shared memory in device buffers
2026-10-05 02:24:51 +04:00
0ee8800905
shader: read image descriptors indexed by workgroup
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Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
0bef3fc0d3
gpu: fix separate alpha blending on swizzled render targets
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Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
a2f851788f
gpu: create texture views before rebinding overlapping images
2026-10-05 02:24:51 +04:00
c3f4962715
shader: use native narrow storage for byte-aligned PS5 buffers
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Co-authored-by: MehmetCambaz <mcambaz18@gmail.com >
2026-10-04 18:39:34 +04:00
Arda Sahin