nmzik
5b826c6e4a
shader: emit native 64-bit operations where compatible
2026-10-05 20:41:03 +04:00
nmzik
7a0e1dafd7
shader: classify native half values with shared operand decoding
2026-10-05 18:39:31 +04:00
nmzik
1d41ddb378
shader: allow RDNA2 SDWA partial destinations for i24 multiply
2026-10-05 18:39:31 +04:00
nmzik
af3011cd69
shader: add missing 64-bit integer image atomics
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-05 04:12:06 +04:00
nmzik
e85279ea7b
shader: correct DS float min/max operands and special values
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-05 04:11:48 +04:00
nmzik
94e7d239dd
gpu: fix zero-source alpha blending on swizzled targets
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Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
nmzik
8274e517b2
shader: add FP64 min, max and rounding
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Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
nmzik
96011cc5c9
gpu: share pipelines when color and alpha blend equations match
2026-10-05 02:24:51 +04:00
nmzik
0bef3fc0d3
gpu: fix separate alpha blending on swizzled render targets
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Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
nmzik
39248a1f87
shader: emit per-vertex mesh clip and cull distances
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Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
nmzik
98557a83b6
shader: implement RDNA2 DS masked OR through shared atomic updates
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
nmzik
efbaa17f71
shader: preserve raw EXEC and VCC bits in 64-bit scalar selects
2026-10-04 18:39:34 +04:00
nmzik
33e74cab2c
test: verify native vector descriptor loads in structured loops
2026-10-04 18:39:34 +04:00
nmzik
b8946fef94
shader: translate RDNA2 signed 64-bit not-equal comparisons
2026-10-04 18:39:34 +04:00
nmzik
b4d32394b6
shader: keep GPU-derived scalar resource reads on the GPU
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
2026-10-04 18:39:34 +04:00
nmzik
284d58d1d5
shader: implement RDNA2 double-precision fractional part
2026-10-04 18:39:34 +04:00
nmzik
d890bb190c
shader: decode RDNA2 bit-reverse SDWA source selectors
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Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
2026-10-04 18:39:34 +04:00
nmzik
ec3e48cdde
shader: synchronize GPU-produced direct writable descriptors
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Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
2026-10-04 18:39:34 +04:00
nmzik
f58014ff0e
shader: preserve wave-wide vector-store completion before publication
2026-10-04 18:39:34 +04:00
nmzik
429d0af62b
shader: bind bounded GPU-selected buffer store destinations
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-04 18:39:34 +04:00
frans
bd611bfe15
Honor explicit gather LOD with shared image mip selection
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Co-authored-by: YuhiAida <21134775+YuhiAida@users.noreply.github.com >
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com >
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-03 14:19:33 +04:00
BlackCAT
ef4c5baf3a
Implement RDNA2 64-bit image atomic maximum
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-03 14:19:32 +04:00
nmzik
64eea6b32d
Reuse vertex shaders across equivalent vertex buffer layouts
2026-10-02 00:51:15 +04:00
nmzik
35759e48cf
shader: expose wave32 feature guards through ballot mask simplification
2026-10-02 00:51:15 +04:00
nmzik
6409be2874
shader: respect branch reachability when refreshing scalar resources
2026-10-02 00:51:15 +04:00
nmzik
11001c97f7
shader: add distinct mesh shader type
2026-10-02 00:51:15 +04:00
nmzik
337f432016
shader: execute PS5 BVH intersections and local FLAT stacks
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Jean-Philippe <github@meunier.jp >
2026-10-02 00:51:15 +04:00
nmzik
64dcbe0ea1
shader: decode the combined conditional-debug branch
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Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com >
2026-10-02 00:51:15 +04:00
nmzik
0ecd32299c
shader: cache registered code identities instead of parsing legacy footers
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Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
2026-10-02 00:51:15 +04:00
nmzik
73615c31ff
graphics: preserve logical alpha when blending reordered targets (PPSA02721)
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Co-authored-by: EmK530 <admin@emk530.net >
2026-09-29 19:52:40 +04:00
nmzik
0fbeac6d3f
graphics: compact shader keys and hash packed pipeline state
2026-09-29 13:57:32 +04:00
nmzik
b43bf9f7fb
graphics: store vertex attribute bindings without duplicated arrays
2026-09-29 13:57:32 +04:00
nmzik
0791f921f6
UFC 5 in-game ( #883 )
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* shader: release descriptor dependencies
* shader: simplify shared-exit control flow
* shader: fix scalar memory loads
* shader: fix LDS counter bounds
* renderer: skip inactive pixel shaders
* shader: respect FP32 mode in comparisons
* renderer: fix sampler border colors
* shader: resolve descriptors from control flow
* shader: resolve descriptors before resource planning
* shader: handle scalar guards for image bounds
* shader: handle reduced guards for image loops
* shader: fix wave guards and material indices
* shader: preserve scalar buffer offset alignment and carry
* shader: prove masked loop bounds across iteration transitions
* shader: preserve source and IR before resource tracking failures
* shader: track material keys selected from active lanes
* shader: remove obsolete post-dominator analysis
* shader: follow bounds guards through control-flow joins
2026-09-28 16:03:05 +04:00
Matthew Hurley
1b6af301b5
tests: wire dormant VOP3 lane-read check and guard new dormant tests ( #840 )
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Tests: enable lane-read coverage and clarify layout failures
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-27 15:37:32 +04:00
Pcniado
bec67b7863
Fix HITMAN 3 boot, layered presentation, and socket imports ( #851 )
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* videoout: synchronize layered flips with premultiplied composition
* shader: support unsigned FFBH subword sources
* shader: apply cube-face result scaling
* shader: prune buffer reads proven out of bounds
* net: implement send and receive exports with shared socket handling
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-27 02:13:30 +04:00
Hamza Shakir
cda236dbb3
Shader recompiler: accept V_NOT_B32 SDWA partial dst with any source; allow 64 buffers
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SDWA source extraction and destination insertion are independent. Cover the reported word1-to-word0 preserve form and byte-source partial destinations in compute tests. Verify 64 distinct compute buffers survive resource tracking and binding layout, and remove the obsolete CFG rejection.
(cherry picked from commit 9e74df7dc0 )
2026-09-26 01:58:55 +04:00
nmzik
6bb68a3fd9
shader: stop repeated CFG merge gateway splitting
2026-09-25 14:27:09 +04:00
nmzik
d72a79af2d
graphics: skip compute dispatches with BVH instructions
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Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
Douglas Soares Silva
fcf0f3b67e
shader: fold the lane test after a pixel shader's entry s_wqm ( #801 )
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Preserve live lane predicates through RDNA2 whole-quad expansion
Keep the source-live predicate when WQM expands a scalar mask, so entry masks remain known live without an instruction pre-scan. Preserve scalar mask values, SCC, half writes, and raw-source behavior.
Cover entry pixel masks, cross-half copies, and scalar/high-word sources with existing shader regression suites.
Co-authored-by: nmzik <Nmzik@mail.ru >
Co-authored-by: Douglas <douglasproducoes21@gmail.com >
2026-09-24 12:02:19 +04:00
nmzik
a6248c7c7c
Convert formatted half-float buffer stores from F32
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Co-authored-by: TarkusR <90155059+TarkusR@users.noreply.github.com >
2026-09-24 11:13:33 +04:00
Deniz ŞAHİN
fc86509aac
shader: support DS_WRITE_B8_D16_HI ( #794 )
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Decode GFX10 DS opcode 0xa0 as DS_WRITE_B8_D16_HI (next to
DS_WRITE_B16_D16_HI at 0xa1) and lower it through the existing 8-bit
shared-memory write. The stored byte is bits 23:16 of the data VGPR,
selected with SDWA BYTE_2 on src1.
Add captured-instruction decode coverage (from GTA V, PPSA04264) and a
runtime regression that writes one byte of a distinctive source value
into a pre-filled LDS dword.
2026-09-24 00:44:39 +04:00
nmzik
7d7267cc56
Translate NGG mesh prolog with guest wave32 width
2026-09-23 22:50:51 +04:00
nmzik
d30dca78be
Read image descriptors in one bounded span
2026-09-23 15:41:02 +04:00
nmzik
03c55e5712
Keep shader user data inline for cached programs
2026-09-23 15:41:02 +04:00
nmzik
13fcb3a133
Refresh cached resources in one SRT walk
2026-09-23 15:41:02 +04:00
nmzik
8dc9b9d532
Persist save allocations for search and mount capacity queries
2026-09-22 11:38:50 +04:00
nmzik
cfb8f7b246
Decode unsigned byte sources for SDWA half-float conversion
2026-09-22 11:11:36 +04:00
nmzik
476204cd4b
Initialize native NGG vertex launch state and wave size
2026-09-22 11:11:36 +04:00
nmzik
f9e56ef8a0
Scope native barriers to shaders with shared execution
2026-09-22 11:11:36 +04:00
Elija
cfb110e0aa
shader: allow partial SDWA destinations for V_NOT_B32 ( #684 )
2026-09-20 18:21:40 +04:00