- Treat tile mode 0x10 as linear when computing a texture layout; it reaches
here from this title and has no tiled interpretation.
- Add the video-out format policies this title asks for.
- Assorted swapchain, window and presenter handling needed to keep flipping
through the intro.
TileManager takes a device buffer per detile and returns it through
DeferDestroy, which cannot run until the GPU retires the tick the free was
queued at. A burst therefore holds every one of those buffers at once, and
nothing bounded the total: measured at 409 MiB across 40 live buffers while an
image allocation was failing 414 MiB short of the budget.
Cap the outstanding scratch and drain the pending-operation queue before taking
more. FlushAndWait alone is not enough - it waits for the GPU but does not pop
the queue, so the frees have not run yet.
The caches decided when to collect from the driver's process-wide usage
estimate, which varied by about 4x between reads of the same moment on this
setup and is not what the allocator is holding. Read VMA's own accounting
instead, and let the collector stand down on the same figure it stood up on
rather than a stale tally.
Adds a small deferral guard so a completion callback cannot re-enter the
resource caches while the caller still holds their state.
Names the upload/stream/download/device-local buffer sizes instead of repeating
literals, and makes the BDA page-table address width explicit.
Two of these are behaviour changes and are the ones to look at:
- DOWNLOAD_BUFFER_SIZE is raised from 32 MiB to 128 MiB. Marvel's Spider-Man:
Miles Morales asks for a single 80 MiB download allocation, which 32 MiB
cannot serve; the run dies with 'failed to map reusable download buffer,
size=0x5000000'. This costs every title the larger reservation.
- CACHING_ADDRESS_BITS is 39, where the table previously covered 40 bits. That
halves the BDA page table from 512 MiB to 256 MiB, at the cost of covering
guest addresses only to 512 GiB. 38 bits was tried first and was too narrow -
it produced an intermittent DMA barrier on an address just past 2^38.
The address-width reduction in particular is tuned against one title; if the
1 TiB window is load-bearing for something else, take the naming and leave the
value at 40.
Tessellation draws were created with a hardcoded 3 control points per patch.
Take the count from VGT_LS_HS_CONFIG.HS_NUM_INPUT_CP instead, and key the
pipeline cache on it so patches of different sizes do not share a pipeline.
* graphics: quiet two misleading render diagnostics
The three PM4 register-offset normalization messages logged once per occurrence with no
limit. They are printed in the colour reserved for problems, and normalizing the offset is
routine, so a short session buries the log in them: PAC-MAN WORLD 2 Re-PAC (PPSA18189)
emitted 24969 of them in about a minute, a fifth of a megabyte and 1.9% of every line
written. Rate-limit all three the way the surrounding diagnostics in these files already
are, which keeps the first occurrences without drowning what follows.
The EQAA check warned whenever a control register was set, including on single-sample
targets where those controls do nothing. That title never multisamples -- all 128 of its
render targets are samples=1 -- yet it still produced the warning, pointing at a cause that
could not apply. Return early when multisampling is off, matching how the neighbouring
sample-location check already reads msaa_num_samples.
Log output only; no rendering behaviour changes.
* graphics: silence normalized offset diagnostics
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Co-authored-by: nmzik <Nmzik@mail.ru>
graphics: stop rejecting valid GE_CNTL group sizes
GE_CNTL group sizes control guest geometry-engine scheduling rather than host wave width. Do not reject the supported vertex path for compiler-selected values above 64, and remove the corresponding stale debug warnings.
Mac