4b651f2ba7
pipeline: fold the program cache into PipelineCache with stable module ids
2026-10-25 02:20:44 +02:00
d7856753e0
shader: walk every resource plan with the x86 SRT walker
2026-10-24 02:57:24 +02:00
286481889f
shader: emit float min/max as host instructions on AMD GPUs ( #1761 )
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* shader: emit float min/max as host instructions on AMD GPUs
V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.
In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.
Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.
Developed with AI assistance (Claude Code).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: gate host float min/max on RADV and check the emitted instructions
* shader: drop float controls 2 from host float min/max
* shader: drop the float min/max env override and atomic flag
* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device
* shader: enable host float min/max on AMD GPUs
---------
Co-authored-by: arda <ardaeska@gmail.com >
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 21:36:08 +02:00
f186b35706
shader: drop null checks on the stage input info pointers
2026-10-20 03:22:40 +02:00
cad6aafdc5
shader: detect and loudly skip unsupported GPU-buffer callables
2026-10-19 05:04:56 +02:00
ab8566591f
shader: link multiple compute helpers without synthetic return loops
2026-10-19 02:34:25 +02:00
c8caa27936
shader: preserve folded native constants for descriptor provenance
2026-10-15 23:22:30 +02:00
50844badbf
shader: map debug SPIR-V blocks to native RDNA2 PCs
2026-10-15 22:28:01 +02:00
302240da70
shader: lower complete wave minima for sparse fragment subgroups
2026-10-14 18:03:48 +02:00
c9ec82e32e
shader: factor live execution guards before resource planning
2026-10-13 21:27:07 +00:00
0e9c77b0a2
shader: bound material selectors by proven one-wave LDS append lists
2026-10-13 21:27:07 +00:00
460a196fca
shader: emit dynamic sample offsets with the enabled maintenance8 feature
2026-10-13 21:27:07 +00:00
3e9f88bf79
shader: isolate SWAPPC work from ordinary shader paths
2026-10-09 17:27:07 +02:00
8c81386568
shader: share finite descriptor planning with GPU-selected inline samplers
2026-10-09 15:06:39 +00:00
bb5edbd490
shader: expose graphics compute queue fields to GETREG
2026-10-09 15:06:39 +00:00
1818aae562
shader: link scalar leaf calls only for SWAPPC programs
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Co-authored-by: Behzad <behzadkhan1736@gmail.com >
2026-10-09 15:06:39 +00:00
e1ac893a0c
shader: collect usage once and emit descriptor slots directly
2026-10-09 02:17:38 +04:00
b0bbaef1eb
gpu: store large compute shared memory in device buffers
2026-10-05 02:24:51 +04:00
3ba0e971e9
shader: materialize exact buffer capacity through shared clean reads
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
8b05b6730e
shader: bind dispatch spans while keeping GPU record counts native
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Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
2026-10-04 18:39:34 +04:00
429d0af62b
shader: bind bounded GPU-selected buffer store destinations
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-04 18:39:34 +04:00
7804eef9b6
Lower finite GPU-selected image descriptors through shared indirect bindings
2026-10-02 15:37:17 +04:00
35759e48cf
shader: expose wave32 feature guards through ballot mask simplification
2026-10-02 00:51:15 +04:00
337f432016
shader: execute PS5 BVH intersections and local FLAT stacks
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Jean-Philippe <github@meunier.jp >
2026-10-02 00:51:15 +04:00
0791f921f6
UFC 5 in-game ( #883 )
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* shader: release descriptor dependencies
* shader: simplify shared-exit control flow
* shader: fix scalar memory loads
* shader: fix LDS counter bounds
* renderer: skip inactive pixel shaders
* shader: respect FP32 mode in comparisons
* renderer: fix sampler border colors
* shader: resolve descriptors from control flow
* shader: resolve descriptors before resource planning
* shader: handle scalar guards for image bounds
* shader: handle reduced guards for image loops
* shader: fix wave guards and material indices
* shader: preserve scalar buffer offset alignment and carry
* shader: prove masked loop bounds across iteration transitions
* shader: preserve source and IR before resource tracking failures
* shader: track material keys selected from active lanes
* shader: remove obsolete post-dominator analysis
* shader: follow bounds guards through control-flow joins
2026-09-28 16:03:05 +04:00
d72a79af2d
graphics: skip compute dispatches with BVH instructions
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Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
5dc644edb4
clean up graphics helpers
2026-09-17 20:35:36 +04:00
a1fbc41146
Preserve shared scalar loads during embedded vertex fetch replacement
2026-09-15 11:24:05 +04:00
87971a28f5
gpu: isolate tessellation analysis and SPIR-V emission
2026-09-14 06:58:32 +04:00
96d62b3367
gpu: reflect tessellation strides from memory address dataflow
2026-09-14 06:58:32 +04:00
7516068662
gpu: compile RDNA2 tessellation through native LS HS and TES stages
2026-09-14 06:58:32 +04:00
e026bfc9a2
shader: let structurization own rollback on failure
2026-09-12 13:42:15 +04:00
5a31de7955
shader: keep derived frontend metadata with its owner
2026-09-12 13:42:15 +04:00
1d1f00bdef
shader: use Khronos definitions and simplify compiler ownership
2026-09-12 13:42:15 +04:00
3902b42096
shader: share direct and conditional branch classification
2026-09-10 14:11:46 +04:00
ef0155636a
shader: support single and split NGG shaders for PPSA11142
2026-09-08 21:26:59 +04:00
72963b01e1
shader: remove redundant decoder and translator state
2026-09-08 21:26:59 +04:00
2c5060e14f
shader: remove masked-value pass and normalize ancillary fields
2026-09-07 11:12:48 +04:00
ace877ce28
shader: lower FMASK loads before binding images
2026-09-06 06:42:23 +04:00
b96a30ed88
shader: keep fragment layer values under lane masks
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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-09-05 11:43:49 +04:00
3213934d42
shader: run merged geometry stages as mesh shaders
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Co-authored-by: Brandon Strong <brandostrong@gmail.com >
Co-authored-by: fxpw <fxpw@outlook.com >
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-09-05 08:32:23 +04:00
fb4d97e8a9
graphics: fix PS5 NGG vertex and instance draw offsets
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Refs: https://github.com/KytyPS5/KytyPS5/issues/130
2026-09-03 21:52:02 +02:00
98200fed19
shader: rework resource specialization and optimize pipeline caching
2026-09-03 03:04:17 +02:00
96c64d113e
shader: trust recompiler stage metadata
2026-08-31 10:30:58 +04:00
66ca225c76
shader: require explicit recompiler resource data
2026-08-31 10:26:08 +04:00
af8aecfdde
shader: remove recompiler error-string propagation
2026-08-31 05:31:41 +04:00
e738535294
graphics: add RDNA2 FLAT BDA buffer cache and faults
2026-08-27 03:45:41 +02:00
ffa69d48de
shader: remove second IR layer
2026-08-26 08:49:39 +02:00
3e25eb0998
Fix wave64 LDS synchronization on subgroup32 hosts
2026-08-23 00:46:37 +02:00
d581703ab4
shader: preserve folded control-flow values
2026-08-22 03:31:59 +02:00
nmzik