6e5167598e
shader: compute add-with-carry with compares and remove IAddCarry32
2026-10-21 22:28:11 +02:00
c571d8ed5a
shader: remove IR opcodes and IREmitter helpers that nothing produces
2026-10-21 22:19:26 +02:00
286481889f
shader: emit float min/max as host instructions on AMD GPUs ( #1761 )
...
* shader: emit float min/max as host instructions on AMD GPUs
V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.
In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.
Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.
Developed with AI assistance (Claude Code).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: gate host float min/max on RADV and check the emitted instructions
* shader: drop float controls 2 from host float min/max
* shader: drop the float min/max env override and atomic flag
* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device
* shader: enable host float min/max on AMD GPUs
---------
Co-authored-by: arda <ardaeska@gmail.com >
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 21:36:08 +02:00
c07ad621f2
graphics: write small GPU-written tiled images back to guest memory behind --readback-tiled-images
...
Co-authored-by: Dimitar Vagalinski <275970482+overlordxrz-source@users.noreply.github.com >
Co-authored-by: Mr. Big Britches <111622360+MrBigBritches@users.noreply.github.com >
2026-10-21 20:55:02 +02:00
13b291f998
gpu: honour DB_ALPHA_TO_MASK as alpha-to-coverage and keep its depth writes behind the shader
2026-10-21 19:17:50 +02:00
7b7294aa03
gpu: drop attachments whose sample count differs from the raster when a draw mixes MSAA and single-sample targets
2026-10-21 19:17:50 +02:00
4644c52927
graphics: initialize BDA tables before first buffer registration
...
Co-authored-by: Leandro Bras <shadowgaming.7@gmail.com >
2026-10-21 05:48:13 +02:00
68d0ba5a81
shader: bound scalar-read overlap checks by the bytes fixed-offset buffer writes reach
2026-10-21 05:48:13 +02:00
70668fbd98
gpu: drop global barriers for PM4 flush events and releases, ordering buffer-writing draws like dispatches
2026-10-21 02:02:25 +02:00
ea1b032c59
shader: drop the unread F32Class bits and the per-pass HS reflection counter reset
2026-10-20 23:54:32 +02:00
3c4124dafa
shader: emit F32 min/max as exact compare-selects, MED3 with one max and saturate as NClamp
2026-10-20 23:36:26 +02:00
8cc5f5364a
shader: share SMEM load results across emulated wave64 halves
2026-10-20 22:32:48 +02:00
1ce663b5a9
shader: lower HS neighbour LDS reads, control-point output read-back, looped HS reflection and integer partitioning
...
Co-authored-by: NeySlim <4509984+NeySlim@users.noreply.github.com >
2026-10-20 22:18:00 +02:00
f492027be2
shader: select pointer-table images through indexed x3 material keys in readlane waterfalls
2026-10-20 15:21:19 +02:00
8843291506
gpu: accept any T# perf_mod on storage textures through a shared canonical encoding check
2026-10-20 15:21:19 +02:00
63ca9c0b80
shader: decode PS5 image_gather4_c_a and image_gather4_c_o_a
2026-10-20 15:21:19 +02:00
c715891242
shader: memoize the tessellation layout per LS/HS pair and VGT configuration
2026-10-20 15:21:19 +02:00
0957f088ad
shader: reflect HS patch constants and lower TES patch inputs through predicated addresses
2026-10-20 15:21:19 +02:00
4a2961cdf9
shader: reflect tessellation strides across forward branches, DS write widths, and packed patch masks
2026-10-20 15:21:19 +02:00
f0e462a8a2
shader: allocate split-wave dispatcher spill IDs in program order
2026-10-20 15:21:19 +02:00
feed075a9f
gpu: implement PA_CL_UCP user clip planes through draw push constants
2026-10-20 15:21:19 +02:00
1a053f9e13
shader: accept dword SETPC tables whose load reuses the selector
2026-10-20 05:11:48 +02:00
f186b35706
shader: drop null checks on the stage input info pointers
2026-10-20 03:22:40 +02:00
fa8216c4d9
shader: size per-thread LDS emulation by the guest LDS allocation
2026-10-20 02:51:27 +02:00
742fe17173
vr: add OpenXR headset output, VR tracker and VR controller input behind --vr ( #1726 )
2026-10-20 02:18:51 +02:00
cd4eab9d65
gpu: clamp resolved buffer ranges to storage buffer limits
2026-10-19 13:53:18 +02:00
fde0b98e69
gpu: preserve zero-stride buffer fetch payloads
2026-10-19 12:23:43 +02:00
d4465faa79
gpu: preserve ordered-append command order
2026-10-19 11:46:39 +02:00
e5f0ee7fc2
gpu: preserve finite buffer descriptors across sparse PRT holes
2026-10-19 05:26:41 +02:00
5f29374d5b
gpu: approximate PPSA24156 EQAA with 2x MSAA and warn once
2026-10-19 05:17:32 +02:00
2c730e58ea
revert HTile lifetime changes and opt-in ZMask support
2026-10-19 05:04:56 +02:00
440245f616
gpu: bound overlapping image copies by both native backings
2026-10-19 05:04:56 +02:00
05d25ef28c
revert 01ce97388: restore compute metadata clear consumption
2026-10-19 05:04:56 +02:00
cad6aafdc5
shader: detect and loudly skip unsupported GPU-buffer callables
2026-10-19 05:04:56 +02:00
defb2f11d3
Share median classifications and preserve RDNA2 signed-zero selection
2026-10-19 02:34:25 +02:00
75d7a4311d
Share repeated SSA bitcasts and guard emitted shader size
2026-10-19 02:34:25 +02:00
bb505a3ae8
Recognize packed descriptor keys in GPU sampler waterfalls
2026-10-19 02:34:25 +02:00
ab8566591f
shader: link multiple compute helpers without synthetic return loops
2026-10-19 02:34:25 +02:00
b2d3ce6dfc
shader: size expanded sampler bindings independently of native roots
2026-10-19 02:34:25 +02:00
09c993dfe0
shader: query dimensions through shared indirect image selection
2026-10-19 02:34:25 +02:00
de81300b28
shader: bound indexed material image selectors before heap expansion
2026-10-19 02:34:25 +02:00
ac3711ce7c
shader: select the primary mip for linear explicit-LOD gathers
2026-10-19 02:34:24 +02:00
8b51370ca1
shader: eliminate predicates for empty branch detours
2026-10-19 02:34:24 +02:00
e9bcc77e0b
shader: retain resource guards for 64-bit scalar comparisons
2026-10-18 20:22:54 +02:00
8639e0de81
shader: share indirect image accesses by type and guard emitted size
2026-10-18 20:16:49 +02:00
099de8dea6
graphics: publish each PM4 WRITE_DATA word exactly once
2026-10-18 16:17:51 +02:00
22ef16a044
shader: implement PS5 vector data cache invalidation
2026-10-18 15:57:14 +02:00
37df7f3278
Show pipeline cache sizes in MB and remove obsolete texture folder cleanup
2026-10-18 03:57:45 +02:00
33208a545a
shader: remove artificial sampled image and sampler pair limit
2026-10-18 03:20:38 +02:00
4059179e9d
graphics: write proven compute buffer fills to guest memory ( #1628 )
...
Avoid readbacks for compute metadata fills
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-18 05:42:14 +02:00
nmzik