Commit Graph

689 Commits

Author SHA1 Message Date
nmzik 79837b423d graphics: support compute stores to 2D MSAA images 2026-10-22 22:11:06 +02:00
nmzik aafe014d0c shader: read raw D16 depth bits through kDepth k16UInt image loads
Co-authored-by: Artyom Zabroda <artyomzabroda@proton.me>
2026-10-22 22:11:06 +02:00
nmzik a358b847c1 graphics: stall waitUntilSafeForRendering in its command processor instead of the GPU thread 2026-10-22 22:11:06 +02:00
nmzik a951a91703 spirv: emit OpName only with debug info 2026-10-22 22:11:06 +02:00
nmzik 86fed10b81 graphics: draw non-indexed and native-fetch indirect draws from GPU-read records 2026-10-22 16:12:20 +02:00
nmzik 949de19bb0 graphics: draw indexed indirect multi-draws from GPU-read arguments 2026-10-22 16:12:20 +02:00
nmzik c513a4a13a graphics: draw single indexed indirect draws from GPU-read arguments 2026-10-22 16:12:20 +02:00
Mr. Big Britches b54057942d texture cache: select color-metadata clears on the GPU with conditional rendering 2026-10-22 16:12:20 +02:00
nmzik 5f5d6effa4 graphics: count DCC/CMASK metadata readbacks in the performance overlay 2026-10-22 16:12:20 +02:00
nmzik c5016d9455 shader: support D16 XY and XYZ formatted buffer loads and stores 2026-10-22 05:26:54 +02:00
Arda Sahin 8502d8a77d image: drop optional create flags the driver rejects instead of aborting (#1760)
* image: request extended usage only for storage images

* tests: restore block-texel-view support through the flag check loop order

---------

Co-authored-by: nmzik <Nmzik@mail.ru>
2026-10-22 03:56:13 +02:00
Nawid3333 919fac13d0 shader: read lane 0 in V_READFIRSTLANE when EXEC is zero instead of an undefined lane 2026-10-22 01:20:54 +02:00
nmzik 11465a5e3c shader: drop the large-input select before sin and cos since fract already returns zero 2026-10-22 00:44:43 +02:00
nmzik 09a9654458 shader: compute DPP permute, rotate, mirror and share lanes with bit-field and XOR ops 2026-10-22 00:40:07 +02:00
nmzik ce54aa8d14 shader: return the first source when both 64-bit min/max inputs are NaN 2026-10-22 00:28:43 +02:00
nmzik 1e4ac1371d shader: return the first source when both float min/max inputs are NaN 2026-10-22 00:00:04 +02:00
nmzik da19501889 shader: translate zero-kind branches as the negated nonzero vote 2026-10-21 23:33:30 +02:00
nmzik fa32940d14 shader: drop BFM mask bits shifted past bit 31 instead of an out-of-range bit-field insert 2026-10-21 22:59:56 +02:00
nmzik aacf15fd0b shader: write preserved SDWA fields with one bit-field insert and drop duplicate 16-bit masks 2026-10-21 22:52:14 +02:00
nmzik 10a852c2ac shader: pack 16-bit lane pairs with one bit-field insert 2026-10-21 22:46:04 +02:00
nmzik 6e5167598e shader: compute add-with-carry with compares and remove IAddCarry32 2026-10-21 22:28:11 +02:00
Arda Sahin 286481889f shader: emit float min/max as host instructions on AMD GPUs (#1761)
* shader: emit float min/max as host instructions on AMD GPUs

V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.

In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.

Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.

Developed with AI assistance (Claude Code).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* shader: gate host float min/max on RADV and check the emitted instructions

* shader: drop float controls 2 from host float min/max

* shader: drop the float min/max env override and atomic flag

* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device

* shader: enable host float min/max on AMD GPUs

---------

Co-authored-by: arda <ardaeska@gmail.com>
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Co-authored-by: nmzik <Nmzik@mail.ru>
2026-10-21 21:36:08 +02:00
nmzik 3c4124dafa shader: emit F32 min/max as exact compare-selects, MED3 with one max and saturate as NClamp 2026-10-20 23:36:26 +02:00
nmzik 1ce663b5a9 shader: lower HS neighbour LDS reads, control-point output read-back, looped HS reflection and integer partitioning
Co-authored-by: NeySlim <4509984+NeySlim@users.noreply.github.com>
2026-10-20 22:18:00 +02:00
nmzik f3e01aaf1e tests: cover tessellation patch constants, predicated mul24 addresses, and forward-branch joins 2026-10-20 15:21:19 +02:00
nmzik fde0b98e69 gpu: preserve zero-stride buffer fetch payloads 2026-10-19 12:23:43 +02:00
shadowbeat070 d4465faa79 gpu: preserve ordered-append command order 2026-10-19 11:46:39 +02:00
nmzik e5f0ee7fc2 gpu: preserve finite buffer descriptors across sparse PRT holes 2026-10-19 05:26:41 +02:00
nmzik 2c730e58ea revert HTile lifetime changes and opt-in ZMask support 2026-10-19 05:04:56 +02:00
Pixeluted 440245f616 gpu: bound overlapping image copies by both native backings 2026-10-19 05:04:56 +02:00
nmzik 05d25ef28c revert 01ce97388: restore compute metadata clear consumption 2026-10-19 05:04:56 +02:00
nmzik defb2f11d3 Share median classifications and preserve RDNA2 signed-zero selection 2026-10-19 02:34:25 +02:00
nmzik 75d7a4311d Share repeated SSA bitcasts and guard emitted shader size 2026-10-19 02:34:25 +02:00
nmzik bb505a3ae8 Recognize packed descriptor keys in GPU sampler waterfalls 2026-10-19 02:34:25 +02:00
nmzik ab8566591f shader: link multiple compute helpers without synthetic return loops 2026-10-19 02:34:25 +02:00
nmzik b2d3ce6dfc shader: size expanded sampler bindings independently of native roots 2026-10-19 02:34:25 +02:00
nmzik 09c993dfe0 shader: query dimensions through shared indirect image selection 2026-10-19 02:34:25 +02:00
nmzik de81300b28 shader: bound indexed material image selectors before heap expansion 2026-10-19 02:34:25 +02:00
nmzik ac3711ce7c shader: select the primary mip for linear explicit-LOD gathers 2026-10-19 02:34:24 +02:00
nmzik 8639e0de81 shader: share indirect image accesses by type and guard emitted size 2026-10-18 20:16:49 +02:00
Santiago Paquete 4059179e9d graphics: write proven compute buffer fills to guest memory (#1628)
Avoid readbacks for compute metadata fills

Co-authored-by: nmzik <Nmzik@mail.ru>
2026-10-18 05:42:14 +02:00
nmzik fe3857a171 graphics: materialize CMASK clears for multisampled targets (PPSA13794) 2026-10-18 02:37:56 +02:00
nmzik c3e7ec8285 graphics: fix Jusant regression from d8c4a9af3 2026-10-18 01:03:37 +02:00
nmzik 763d3be3a9 graphics: add opt-in ZMask support and launcher rendering options 2026-10-17 17:50:02 +02:00
nmzik d8c4a9af38 graphics: preserve HTILE metadata across native image replacement 2026-10-17 17:31:25 +02:00
nmzik 9f88043ebe shader: use compact integer RTZ half conversion 2026-10-17 12:23:12 +02:00
nmzik 5bf37f52ad renderer: clear compressed stencil with pending depth metadata 2026-10-17 09:50:11 +02:00
nmzik 57791645e4 renderer: track attachment load clears by image aspect 2026-10-17 09:34:51 +02:00
nmzik d1fe1324c8 shader: keep coherent 64bit atomic 2026-10-17 07:52:20 +02:00
Nawid3333 b82512be06 shader: read float inline constants on 64-bit operands as f64 bits (#1576)
A float inline constant (240-248) read by a 64-bit operand is the f64 bit
pattern for integer B64 opcodes too: AMD's compilers emit
v_lshrrev_b64 v[4:5], v0, 1.0 for 0x3ff0000000000000 >> lane. ReadU32Pair
returned {f32 bits, 0}, so only F64-typed reads had the right value.

Based on TheCruZ's 284deab28 (closed #1219).

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-17 05:21:06 +02:00