919fac13d0
shader: read lane 0 in V_READFIRSTLANE when EXEC is zero instead of an undefined lane
2026-10-22 01:20:54 +02:00
a52d1ed4e2
shader: drop the 64-bit min/max NaN-lhs select the ordered compare already covers
2026-10-22 01:09:09 +02:00
2b37dee2b7
shader: track possible bits through bit-field inserts in resource tracking
2026-10-22 01:08:07 +02:00
a3aece2762
shader: check the DPP source lane bound only for row shifts
2026-10-22 01:02:38 +02:00
64186404a3
shader: load the DPP lane id once for both partial write masks
2026-10-22 01:01:38 +02:00
11465a5e3c
shader: drop the large-input select before sin and cos since fract already returns zero
2026-10-22 00:44:43 +02:00
09a9654458
shader: compute DPP permute, rotate, mirror and share lanes with bit-field and XOR ops
2026-10-22 00:40:07 +02:00
6123419437
shader: skip full DPP row and bank masks and test partial ones with one bit extract
2026-10-22 00:35:09 +02:00
8177969f33
shader: branch to the pixel kill on the inverted targets instead of negating the condition
2026-10-22 00:33:07 +02:00
6ee2ef8715
shader: insert the V_CVT_PK_U8_F32 byte with one bit-field insert
2026-10-22 00:31:52 +02:00
9e4234cdbe
shader: extract the V_CVT_F32_UBYTE source byte with one bit-field extract
2026-10-22 00:30:39 +02:00
ce54aa8d14
shader: return the first source when both 64-bit min/max inputs are NaN
2026-10-22 00:28:43 +02:00
2d00e13bf3
shader: rely on the saturating float-to-int conversion instead of re-saturating in the translator
2026-10-22 00:26:40 +02:00
3bb09ed2a4
shader: clamp before float-to-int conversion and drop the redundant truncate
2026-10-22 00:26:40 +02:00
1e4ac1371d
shader: return the first source when both float min/max inputs are NaN
2026-10-22 00:00:04 +02:00
9c39062d3e
shader: double the cube major axis once after selecting the face
2026-10-21 23:56:13 +02:00
93071ebdf8
shader: drop the denormal flush before exp2
2026-10-21 23:33:42 +02:00
3a842e1a6b
shader: flush FP32 denormals with a float compare and multiply instead of bit masks
2026-10-21 23:33:42 +02:00
da19501889
shader: translate zero-kind branches as the negated nonzero vote
2026-10-21 23:33:30 +02:00
0f7d112545
shader: emit constant-true guarded blocks inline and fold immediate constant-buffer indices
2026-10-21 23:27:04 +02:00
ae47ac26e7
shader: compute scalar signed-overflow SCC with compares instead of XOR masks
2026-10-21 23:27:04 +02:00
7c40dbc36c
shader: build the S_BFE_U64 mask from clamped halves and remove RightMask64
2026-10-21 23:16:17 +02:00
0cdc5c1224
shader: build the V_MBCNT lanes-below mask with the shared right-mask helper
2026-10-21 23:11:26 +02:00
fa32940d14
shader: drop BFM mask bits shifted past bit 31 instead of an out-of-range bit-field insert
2026-10-21 22:59:56 +02:00
2862ad5b25
shader: compute scalar signed-overflow and shift-add carry SCC with fewer ops
2026-10-21 22:56:21 +02:00
aacf15fd0b
shader: write preserved SDWA fields with one bit-field insert and drop duplicate 16-bit masks
2026-10-21 22:52:14 +02:00
10a852c2ac
shader: pack 16-bit lane pairs with one bit-field insert
2026-10-21 22:46:04 +02:00
4a1440197f
shader: share one find-first-bit lowering for S_FF0/FF1/FLBIT_I32_B64 and remove FindUMsb64
2026-10-21 22:39:34 +02:00
6e5167598e
shader: compute add-with-carry with compares and remove IAddCarry32
2026-10-21 22:28:11 +02:00
c571d8ed5a
shader: remove IR opcodes and IREmitter helpers that nothing produces
2026-10-21 22:19:26 +02:00
286481889f
shader: emit float min/max as host instructions on AMD GPUs ( #1761 )
...
* shader: emit float min/max as host instructions on AMD GPUs
V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.
In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.
Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.
Developed with AI assistance (Claude Code).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: gate host float min/max on RADV and check the emitted instructions
* shader: drop float controls 2 from host float min/max
* shader: drop the float min/max env override and atomic flag
* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device
* shader: enable host float min/max on AMD GPUs
---------
Co-authored-by: arda <ardaeska@gmail.com >
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 21:36:08 +02:00
68d0ba5a81
shader: bound scalar-read overlap checks by the bytes fixed-offset buffer writes reach
2026-10-21 05:48:13 +02:00
ea1b032c59
shader: drop the unread F32Class bits and the per-pass HS reflection counter reset
2026-10-20 23:54:32 +02:00
3c4124dafa
shader: emit F32 min/max as exact compare-selects, MED3 with one max and saturate as NClamp
2026-10-20 23:36:26 +02:00
8cc5f5364a
shader: share SMEM load results across emulated wave64 halves
2026-10-20 22:32:48 +02:00
1ce663b5a9
shader: lower HS neighbour LDS reads, control-point output read-back, looped HS reflection and integer partitioning
...
Co-authored-by: NeySlim <4509984+NeySlim@users.noreply.github.com >
2026-10-20 22:18:00 +02:00
f492027be2
shader: select pointer-table images through indexed x3 material keys in readlane waterfalls
2026-10-20 15:21:19 +02:00
63ca9c0b80
shader: decode PS5 image_gather4_c_a and image_gather4_c_o_a
2026-10-20 15:21:19 +02:00
0957f088ad
shader: reflect HS patch constants and lower TES patch inputs through predicated addresses
2026-10-20 15:21:19 +02:00
4a2961cdf9
shader: reflect tessellation strides across forward branches, DS write widths, and packed patch masks
2026-10-20 15:21:19 +02:00
f0e462a8a2
shader: allocate split-wave dispatcher spill IDs in program order
2026-10-20 15:21:19 +02:00
feed075a9f
gpu: implement PA_CL_UCP user clip planes through draw push constants
2026-10-20 15:21:19 +02:00
1a053f9e13
shader: accept dword SETPC tables whose load reuses the selector
2026-10-20 05:11:48 +02:00
f186b35706
shader: drop null checks on the stage input info pointers
2026-10-20 03:22:40 +02:00
fa8216c4d9
shader: size per-thread LDS emulation by the guest LDS allocation
2026-10-20 02:51:27 +02:00
cad6aafdc5
shader: detect and loudly skip unsupported GPU-buffer callables
2026-10-19 05:04:56 +02:00
defb2f11d3
Share median classifications and preserve RDNA2 signed-zero selection
2026-10-19 02:34:25 +02:00
75d7a4311d
Share repeated SSA bitcasts and guard emitted shader size
2026-10-19 02:34:25 +02:00
bb505a3ae8
Recognize packed descriptor keys in GPU sampler waterfalls
2026-10-19 02:34:25 +02:00
ab8566591f
shader: link multiple compute helpers without synthetic return loops
2026-10-19 02:34:25 +02:00
Nawid3333