286481889f
shader: emit float min/max as host instructions on AMD GPUs ( #1761 )
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* shader: emit float min/max as host instructions on AMD GPUs
V_MIN_F32, V_MAX_F32, V_MIN3_F32 and V_MAX3_F32 were emulated with a
classify-and-select sequence of about a dozen instructions each, to give
the guest's NaN and signed-zero results on any host. AMD GPUs execute
GLSL.std.450 NMin/NMax with those same rules, so emit them directly when
the device is AMD and supports VK_KHR_shader_float_controls2. Each
instruction is decorated FPFastMathMode None, since
SignedZeroInfNanPreserve does not cover extended instructions. MED3 keeps
its exact emulation. KYTY_EMULATED_FLOAT_MIN_MAX=1 keeps the emulation.
In SAROS the two heaviest compute shaders get 37% and 59% faster on an
RX 9070 XT (RADV), about 4 ms of GPU time per frame.
Adds VectorMinMaxF32RuntimeEdges (runtime operands, so nothing is folded)
and a --float-min-max-only mode that runs it and
VectorMinMaxF32NanAndSignedZeroEdges with the emulation and, where
supported, with host instructions.
Developed with AI assistance (Claude Code).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: gate host float min/max on RADV and check the emitted instructions
* shader: drop float controls 2 from host float min/max
* shader: drop the float min/max env override and atomic flag
* shader: pass host capabilities to the SPIR-V emitter as a profile built once per device
* shader: enable host float min/max on AMD GPUs
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Co-authored-by: arda <ardaeska@gmail.com >
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-21 21:36:08 +02:00
c07ad621f2
graphics: write small GPU-written tiled images back to guest memory behind --readback-tiled-images
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Co-authored-by: Dimitar Vagalinski <275970482+overlordxrz-source@users.noreply.github.com >
Co-authored-by: Mr. Big Britches <111622360+MrBigBritches@users.noreply.github.com >
2026-10-21 20:55:02 +02:00
13b291f998
gpu: honour DB_ALPHA_TO_MASK as alpha-to-coverage and keep its depth writes behind the shader
2026-10-21 19:17:50 +02:00
7b7294aa03
gpu: drop attachments whose sample count differs from the raster when a draw mixes MSAA and single-sample targets
2026-10-21 19:17:50 +02:00
4644c52927
graphics: initialize BDA tables before first buffer registration
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Co-authored-by: Leandro Bras <shadowgaming.7@gmail.com >
2026-10-21 05:48:13 +02:00
68d0ba5a81
shader: bound scalar-read overlap checks by the bytes fixed-offset buffer writes reach
2026-10-21 05:48:13 +02:00
70668fbd98
gpu: drop global barriers for PM4 flush events and releases, ordering buffer-writing draws like dispatches
2026-10-21 02:02:25 +02:00
8843291506
gpu: accept any T# perf_mod on storage textures through a shared canonical encoding check
2026-10-20 15:21:19 +02:00
feed075a9f
gpu: implement PA_CL_UCP user clip planes through draw push constants
2026-10-20 15:21:19 +02:00
cd4eab9d65
gpu: clamp resolved buffer ranges to storage buffer limits
2026-10-19 13:53:18 +02:00
fde0b98e69
gpu: preserve zero-stride buffer fetch payloads
2026-10-19 12:23:43 +02:00
d4465faa79
gpu: preserve ordered-append command order
2026-10-19 11:46:39 +02:00
e5f0ee7fc2
gpu: preserve finite buffer descriptors across sparse PRT holes
2026-10-19 05:26:41 +02:00
5f29374d5b
gpu: approximate PPSA24156 EQAA with 2x MSAA and warn once
2026-10-19 05:17:32 +02:00
2c730e58ea
revert HTile lifetime changes and opt-in ZMask support
2026-10-19 05:04:56 +02:00
440245f616
gpu: bound overlapping image copies by both native backings
2026-10-19 05:04:56 +02:00
05d25ef28c
revert 01ce97388: restore compute metadata clear consumption
2026-10-19 05:04:56 +02:00
cad6aafdc5
shader: detect and loudly skip unsupported GPU-buffer callables
2026-10-19 05:04:56 +02:00
ab8566591f
shader: link multiple compute helpers without synthetic return loops
2026-10-19 02:34:25 +02:00
b2d3ce6dfc
shader: size expanded sampler bindings independently of native roots
2026-10-19 02:34:25 +02:00
37df7f3278
Show pipeline cache sizes in MB and remove obsolete texture folder cleanup
2026-10-18 03:57:45 +02:00
4059179e9d
graphics: write proven compute buffer fills to guest memory ( #1628 )
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Avoid readbacks for compute metadata fills
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-18 05:42:14 +02:00
fe3857a171
graphics: materialize CMASK clears for multisampled targets (PPSA13794)
2026-10-18 02:37:56 +02:00
c3e7ec8285
graphics: fix Jusant regression from d8c4a9af3
2026-10-18 01:03:37 +02:00
763d3be3a9
graphics: add opt-in ZMask support and launcher rendering options
2026-10-17 17:50:02 +02:00
d8c4a9af38
graphics: preserve HTILE metadata across native image replacement
2026-10-17 17:31:25 +02:00
6aa3846fb2
feat: add an in-game performance panel ( #1090 )
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Add in-game performance panel
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-17 14:47:51 +02:00
5bf37f52ad
renderer: clear compressed stencil with pending depth metadata
2026-10-17 09:50:11 +02:00
57791645e4
renderer: track attachment load clears by image aspect
2026-10-17 09:34:51 +02:00
9202bddad2
recognize verified pattern fills
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Co-authored-by: Juan Pablo Farias <juanpablo.profissional.a.f@gmail.com >
2026-10-17 04:09:54 +02:00
b899717900
renderer: log unsupported depth feedback once
2026-10-16 17:24:45 +02:00
d58aefde49
renderer: reduce synchronization and allocation overhead
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Performance changes from #1495 :
- Sync changed BDA ranges instead of scanning all mappings.
- Let VMA suballocate BDA buffers.
- Remove the renderer lock from presentation.
- Keep compatible pipeline caches across builds.
- Fold masked shifts that always produce zero.
2026-10-16 17:18:49 +02:00
f7226ca7dc
graphics: emit PS5 register object and primitive IDs to RT7
2026-10-15 22:28:01 +02:00
bcf13e101e
shader: validate texture mip ranges and channel selectors
2026-10-15 22:28:01 +02:00
959bee4799
graphics: checkpoint live Vulkan pipeline cache after new compilations
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
b4406b0467
graphics: render packed 11-11-10 UNorm targets with exact rounding
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
87d938139d
graphics: log complete per-target state before format resolution
2026-10-15 22:28:01 +02:00
279bc95941
graphics: track HTile clears across PS5 depth array slices
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:01 +02:00
12c522bba5
graphics: log cached GPU completion beside dispatch submission ticks
2026-10-15 22:28:01 +02:00
50844badbf
shader: map debug SPIR-V blocks to native RDNA2 PCs
2026-10-15 22:28:01 +02:00
8b81f665a2
shader: separate indirect buffer candidates from tracked root limits
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 21:19:38 +02:00
ceccd746d8
shader: resolve workgroup-selected descriptor prefixes from dispatch arguments
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 20:29:48 +02:00
892e70c8a1
graphics: bind unbound textures as native null descriptors
2026-10-14 17:56:47 +02:00
3a925efddf
graphics: preserve sparse spans in rebased mip-tail views
2026-10-14 16:07:49 +02:00
8c7fe539b8
graphics: represent rebased contiguous mip-tail texture views
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 15:56:45 +02:00
c88f05f7b5
graphics: share signed storage conversion and support R16 image writes
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 15:36:29 +02:00
be5915c248
graphics: skip GPU-clean empty indirect dispatches before shader preparation
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Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 03:36:33 +02:00
01ce973882
renderer: preserve guest writes to reused metadata buffers
2026-10-13 21:33:50 +00:00
3c9da9c3f4
graphics: decode both channels of RG32 float metadata clears
2026-10-13 21:33:50 +00:00
ff6dffe298
graphics: decode packed unsigned float CMASK register clears
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Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-13 21:33:50 +00:00
Arda Sahin